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    APPARATUS WITH REDUNDANT CIRCUITRY AND METHOD THEREFOR
    8.
    发明申请
    APPARATUS WITH REDUNDANT CIRCUITRY AND METHOD THEREFOR 有权
    具有冗余电路的装置及其方法

    公开(公告)号：US20100017652A1

    公开(公告)日：2010-01-21

    申请号：US12509803

    申请日：2009-07-27

    申请人： Michael Mantor ,  Ralph Clayton Taylor ,  Robert Scott Hartog

    发明人： Michael Mantor ,  Ralph Clayton Taylor ,  Robert Scott Hartog

    IPC分类号： G06F11/20

    CPC分类号： G06F11/2028 ,  G06F11/2038 ,  G06F11/2048

    摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

    摘要翻译： 具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。 输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。 当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。 冗余的并行ALU然后对有缺陷的ALU进行操作。 输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于 由其他电路进一步处理。

    Method and apparatus for dual pass adaptive tessellation
    9.
    发明授权
    Method and apparatus for dual pass adaptive tessellation 有权
    用于双通道自适应细分的方法和装置

    公开(公告)号：US07423644B2

    公开(公告)日：2008-09-09

    申请号：US11428756

    申请日：2006-07-05

    申请人： Vineet Goel ,  Stephen L. Morein ,  Robert Scott Hartog

    发明人： Vineet Goel ,  Stephen L. Morein ,  Robert Scott Hartog

    IPC分类号： G06T15/30

    CPC分类号： G06T17/20 ,  G06T15/005 ,  G06T2200/28

    摘要： A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

    摘要翻译： 用于双通道适应性镶嵌的方法和装置包括可操作地耦合以接收原始信息的顶点石斑鱼细分器和索引列表以及耦合到顶点石斑鱼细分器的着色器处理单元。 在第一次通过期间，着色器处理单元接收从原始信息生成的原始索引和多个基元索引中的每一个的自动索引值。 所述方法和装置还包括可操作地耦合到着色器序列的多个顶点着色器输入暂存寄存器，其中多个顶点着色器输入暂存寄存器耦合到多个顶点着色器，使得响应于着色器序列输出，顶点 着色器产生细分因素。 将细分因子提供给顶点分组器细分器，使得顶点分割器细分器在第二遍期间生成每个进程向量输出，每个基元输出和每个分组输出。