-
公开(公告)号：US07386765B2
公开(公告)日：2008-06-10
申请号：US10674320
申请日：2003-09-29
CPC分类号： G06F11/1044
摘要： Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
摘要翻译： 在存储器总线上没有活动的情况下，与存储器控制器独立地对存储器件内的存储器错误执行检查的装置和方法，该存储器总线将存储器装置耦合到涉及存储器件的存储器控制器。
-
公开(公告)号：US07353329B2
公开(公告)日：2008-04-01
申请号：US10674981
申请日：2003-09-29
申请人： Robert M. Ellis , Kuljit S. Bains , Chris B. Freeman , John B. Halbert , Narendra S. Khandekar , Michael W. Williams
发明人： Robert M. Ellis , Kuljit S. Bains , Chris B. Freeman , John B. Halbert , Narendra S. Khandekar , Michael W. Williams
IPC分类号： G06F12/16
CPC分类号： G11C11/406 , G06F13/1636 , G11C2211/4061
摘要： Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
摘要翻译： 在存储器总线上没有活动的情况下，独立于存储器控制器，在与存储器件相关联的存储器控制器的存储器总线的时间内，独立于存储器控制器，在存储器件中的行存储器单元上执行刷新操作的装置和方法。
-
3.发明授权Method and apparatus for providing debug functionality in a buffered memory channel 失效用于在缓冲存储器通道中提供调试功能的方法和装置公开(公告)号：US06996749B1
公开(公告)日：2006-02-07
申请号：US10713564
申请日：2003-11-13
IPC分类号： G06F11/00
CPC分类号： G11C29/48 , G11C29/56 , G11C2029/5602
摘要： Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.
摘要翻译： 本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。 一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。 在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。 其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。 在权利要求中描述了其它实施例。
-
公开(公告)号：US06421280B1
公开(公告)日：2002-07-16
申请号：US09583951
申请日：2000-05-31
申请人： Robert M. Ellis
发明人： Robert M. Ellis
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G06F12/0859 , G11C7/1078
摘要： A method and circuit are provided for asynchronously loading data in a first data buffer and a second data buffer and synchronously reading the data from the first data buffer and the second data buffer. A load data circuit may receive a plurality of input signals and output a first latch enable signal and a second latch enable signal. The load data circuit may asynchronously operate based on the input signals. The first latch enable signal may enable data to be loaded in the first data buffer and the second latch enable signal may enable data to be loaded in the second data buffer. A read data circuit may be coupled to the first data buffer and the second data buffer. The read data circuit may synchronously address the first data buffer and said second data buffer so as to read the data based on a synchronous clock signal.
摘要翻译： 提供了一种用于在第一数据缓冲器和第二数据缓冲器中异步加载数据并同步地从第一数据缓冲器和第二数据缓冲器读取数据的方法和电路。 负载数据电路可以接收多个输入信号并输出第一锁存使能信号和第二锁存使能信号。 负载数据电路可以基于输入信号异步工作。 第一锁存使能信号可以使得能够将数据加载到第一数据缓冲器中，而第二锁存使能信号可使数据能够加载到第二数据缓冲器中。 读数据电路可以耦合到第一数据缓冲器和第二数据缓冲器。 读取数据电路可以同步地寻址第一数据缓冲器和第二数据缓冲器，以便基于同步时钟信号来读取数据。
-
5.发明授权公开(公告)号：US07721060B2
公开(公告)日：2010-05-18
申请号：US10713563
申请日：2003-11-13
申请人： Robert M. Ellis
发明人： Robert M. Ellis
CPC分类号： G06F13/4234 , G06F13/4256 , H04L7/033
摘要： Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.
摘要翻译： 本发明的一些实施例实现点对点存储器通道，其通过跟踪入站和出站数据通道上的数据转换的数量实际上消除了对于导出的定时架构的强制同步周期的需要，以确保发生最小数量的转换。 本发明的其他实施例执行数据反转以增加满足最小数据转换密度的可能性。 在权利要求中描述了其它实施例。
-
公开(公告)号：US07050351B2
公开(公告)日：2006-05-23
申请号：US10750038
申请日：2003-12-30
IPC分类号： G11C8/00
CPC分类号： G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C11/4096 , G11C2207/005
摘要： Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.
摘要翻译： 提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问内容读取内容 通过读取操作使至少一行直接从存储器单元行读取数据从读出放大器行读取。
-
7.发明授权Method and apparatus for providing debug functionality in a buffered memory channel 有权用于在缓冲存储器通道中提供调试功能的方法和装置公开(公告)号：US07412627B2
公开(公告)日：2008-08-12
申请号：US11192249
申请日：2005-07-27
IPC分类号： G06F11/00
CPC分类号： G11C29/48 , G11C29/56 , G11C2029/5602
摘要： Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.
摘要翻译： 本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。 一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。 在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。 其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。 在权利要求中描述了其它实施例。
-
8.发明授权公开(公告)号：US07243205B2
公开(公告)日：2007-07-10
申请号：US10713784
申请日：2003-11-13
申请人： Chris B. Freeman , Pete D. Vogt , Kuljit S. Bains , Robert M. Ellis , John B. Halbert , Michael W. Williams
发明人： Chris B. Freeman , Pete D. Vogt , Kuljit S. Bains , Robert M. Ellis , John B. Halbert , Michael W. Williams
IPC分类号： G06F12/00
CPC分类号： G06F13/16
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.
摘要翻译： 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。 缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作 。 例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。 描述和要求保护其他实施例。
-
公开(公告)号：US07085152B2
公开(公告)日：2006-08-01
申请号：US10748460
申请日：2003-12-29
IPC分类号： G11C11/24
CPC分类号： G11C11/406 , G11C5/14 , G11C11/4074 , G11C2207/104 , G11C2211/4067
摘要： A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.
摘要翻译： 具有被提供有比提供给存储器逻辑的单独功率分开的更高电压功率的存储单元的存储器件，以及需要从逻辑中的至少一些去除功率的较低功率状态，使得刷新操作以保持存储器单元的内容 继续发生，但至少有一些到存储器件的接口掉电以降低功耗。
-
公开(公告)号：US06990036B2
公开(公告)日：2006-01-24
申请号：US10749690
申请日：2003-12-30
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G06F12/0893 , G06F2212/3042 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C2207/005 , Y02D10/13
摘要： Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.
摘要翻译： 提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问写入数据 通过写入操作指向至少一行，使得数据直接从存储单元行写入读出放大器行，并存储由读出放大器行缓冲的数据变脏的指示。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.021 秒)
