发明授权
US07721060B2 Method and apparatus for maintaining data density for derived clocking
有权
用于保持导出时钟的数据密度的方法和装置
- 专利标题: Method and apparatus for maintaining data density for derived clocking
- 专利标题(中): 用于保持导出时钟的数据密度的方法和装置
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申请号: US10713563申请日: 2003-11-13
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公开(公告)号: US07721060B2公开(公告)日: 2010-05-18
- 发明人: Robert M. Ellis
- 申请人: Robert M. Ellis
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Marger Johnson & McCollom, P.C.
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F13/00
摘要:
Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.
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