公开(公告)号：US06274424B1

公开(公告)日：2001-08-14

申请号：US09602785

申请日：2000-06-23

申请人： Bruce E. White, Jr. ,  Robert Edwin Jones, Jr.

发明人： Bruce E. White, Jr. ,  Robert Edwin Jones, Jr.

IPC分类号： H01L218244

CPC分类号： H01L27/10852 ,  H01L21/76807 ,  H01L21/76895 ,  H01L27/10873 ,  H01L28/55 ,  H01L28/60

摘要： A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.

摘要翻译： 通过形成双重镶嵌区域（34a至34c）开始形成具有CMOS逻辑部分的芯片上的改进的嵌入式DRAM结构的方法。 区域（34a）是双重镶嵌区域的一部分，其填充有耐氧化材料（例如铱或钌）以形成金属塞（36a）。 该插头（36a）形成用于DRAM的存储节点区域，并与DRAM传输晶体管的电流电极（26）电接触。 开口（34b）与开口（34a）的填充同时填充，以形成形成DRAM单元的位线接触的金属插塞（36b）。 双重镶嵌结构（34c）的顶部与区域（34a和34b）同时填充，以形成铁电DRAM电容器的底部电极。 由于区域（36c）的几何形状由双重镶嵌/ CMP处理限定，所以不存在底部电容器电极的RIE限定的侧壁，从而降低了电容器漏电流。 此外，用于形成塞子（36a至36c）的耐氧材料在此防止了在铁电氧退火期间现有技术中存在的不利的塞子氧化。

公开(公告)号：US6130102A

公开(公告)日：2000-10-10

申请号：US963443

申请日：1997-11-03

申请人： Bruce E. White, Jr. ,  Robert Edwin Jones, Jr.

发明人： Bruce E. White, Jr. ,  Robert Edwin Jones, Jr.

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01G7/06

CPC分类号： H01L27/10852 ,  H01L27/10873 ,  H01L28/60 ,  H01L21/76807 ,  H01L21/76895 ,  H01L28/55

摘要： A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.

摘要翻译： 通过形成双重镶嵌区域（34a至34c）开始形成具有CMOS逻辑部分的芯片上的改进的嵌入式DRAM结构的方法。 区域（34a）是双重镶嵌区域的一部分，其填充有耐氧化材料（例如铱或钌）以形成金属塞（36a）。 该插头（36a）形成用于DRAM的存储节点区域，并与DRAM传输晶体管的电流电极（26）电接触。 开口（34b）与开口（34a）的填充同时填充，以形成形成DRAM单元的位线接触的金属插塞（36b）。 双重镶嵌结构（34c）的顶部与区域（34a和34b）同时填充，以形成铁电DRAM电容器的底部电极。 由于区域（36c）的几何形状由双重镶嵌/ CMP处理限定，所以不存在底部电容器电极的RIE限定的侧壁，从而降低了电容器漏电流。 此外，用于形成塞子（36a至36c）的耐氧材料在此防止了在铁电氧退火期间现有技术中存在的不利的塞子氧化。

公开(公告)号：US5696394A

公开(公告)日：1997-12-09

申请号：US664327

申请日：1996-06-14

申请人： Robert Edwin Jones, Jr. ,  Papu D. Maniar ,  Andrew C. Campbell ,  Reza Moazzami

发明人： Robert Edwin Jones, Jr. ,  Papu D. Maniar ,  Andrew C. Campbell ,  Reza Moazzami

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L29/92

CPC分类号： H01L27/10808 ,  H01L28/55

摘要： A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

摘要翻译： 具有金属氧化物电介质层的电容器形成有电连接到下面的电路元件的上电极层。 电容器可用于形成用于DRAM和NVRAM单元的存储电容器。 在形成诸如晶体管的源极/漏极区域的底层电路元件之后，在电路元件上形成金属氧化物电容器。 通过电容器形成开口并延伸到电路元件。 形成绝缘间隔物，并且形成将电路元件与金属氧化物电容器的上电极层电连接的导电部件。 公开了包括DRAM和NVRAM单元的器件及其形成方法。