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    Network media access controller embedded in a programmable logic device—host interface control generator
    1.
    发明授权
    Network media access controller embedded in a programmable logic device—host interface control generator 有权
    网络媒体接入控制器嵌入可编程逻辑器件 - 主机接口控制发生器

    公开(公告)号：US07376774B1

    公开(公告)日：2008-05-20

    申请号：US11040136

    申请日：2005-01-21

    申请人： Robert Yin ,  Richard P. Burnley

    发明人： Robert Yin ,  Richard P. Burnley

    IPC分类号： G06F13/00 ,  G06F12/10

    CPC分类号： H04L12/56 ,  H04J3/0697 ,  H04L45/60

    摘要： Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

    摘要翻译： 描述了用于媒体访问控制器的地址过滤的方法和装置。 位于可编程逻辑器件中的专用集成电路块包括媒体访问控制器。 媒体访问控制器包括地址过滤器，其包括：地址过滤器模块，耦合到每个地址过滤器模块的第一逻辑树，并且被配置为提供用于在丢弃的帧和地址过滤的帧之间进行描绘的帧丢弃信号; 以及耦合到每个地址过滤器模块以提供地址有效信号的第二逻辑树。

    Timing performance analysis
    2.
    发明授权
    Timing performance analysis 有权
    定时性能分析

    公开(公告)号：US06934922B1

    公开(公告)日：2005-08-23

    申请号：US10084515

    申请日：2002-02-27

    申请人： Richard P. Burnley

    发明人： Richard P. Burnley

    IPC分类号： G06F9/45 ,  G06F11/34 ,  G06F17/50 ,  H03K19/00

    CPC分类号： G06F11/3466 ,  G06F17/5031

    摘要： Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.

    摘要翻译： 描述了确定到达和来自嵌入式设备的路径时序的方法。 更具体地，可应用地获得并确定时钟到输出延迟，互连和互连逻辑延迟以及来自微处理器核心和存储器控制器的输入和输出路径的建立和保持时间。 这些时间被组装在用于与各个信号相关联的电子表格中。 每个信号的时间被合计以确定用于与目标时钟周期进行比较的各个路径延迟。

    Network media access controller embedded in a programmable logic device—address filter
    3.
    发明授权
    Network media access controller embedded in a programmable logic device—address filter 有权
    嵌入在可编程逻辑器件地址过滤器中的网络介质访问控制器

    公开(公告)号：US07421528B1

    公开(公告)日：2008-09-02

    申请号：US11590579

    申请日：2006-10-31

    申请人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant

    发明人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant

    IPC分类号： G06F13/00 ,  G06F12/00 ,  H04L12/54

    CPC分类号： H04L12/56 ,  H04J3/0697 ,  H04L45/60

    摘要： A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.

    摘要翻译： 描述地址过滤的方法。 提供了包括设备寄存器的主机接口。 启动用户程序，将数据和控制信息分别装载到设备寄存器的第一数据寄存器和控制寄存器中。 响应于加载，开始硬件将加载到第一数据寄存器中的信息写入主机接口寄存器，其中第一数据寄存器与地址表配置条目相关联，并且该信息包括读或写信息和地址信息。 响应于读或写信息和地址信息，从存储获得多播地址; 多播地址的第一部分被存入第一数据寄存器; 多播地址的第二部分被存入第二数据寄存器。

    Buffered asynchronous communications elements with receive/transmit control and status reporting
    4.
    发明授权
    Buffered asynchronous communications elements with receive/transmit control and status reporting 失效
    具有接收/发送控制和状态报告的缓冲异步通信元件

    公开(公告)号：US5287458A

    公开(公告)日：1994-02-15

    申请号：US38713

    申请日：1993-03-26

    申请人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

    发明人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

    IPC分类号： H04L25/45 ,  G06F13/12

    CPC分类号： H04L25/45

    摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

    摘要翻译： 用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。 异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO， 以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。 发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。 接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。 接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。 接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

    Buffered asynchronous communications element with receive/transmit control and status reporting
    5.
    发明授权
    Buffered asynchronous communications element with receive/transmit control and status reporting 失效
    具有接收/发送控制和状态报告的缓冲异步通信元件

    公开(公告)号：US5241660A

    公开(公告)日：1993-08-31

    申请号：US703572

    申请日：1991-05-17

    申请人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

    发明人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

    IPC分类号： H04L25/45

    CPC分类号： H04L25/45

    摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

    摘要翻译： 用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。 异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO， 以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。 发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。 接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。 接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。 接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

    Asynchronous communications element
    6.
    发明授权
    Asynchronous communications element 失效
    异步通信元件

    公开(公告)号：US4823312A

    公开(公告)日：1989-04-18

    申请号：US924797

    申请日：1986-10-30

    申请人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

    发明人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

    IPC分类号： H04L25/45 ,  H04Q9/00 ,  G06F3/04 ,  H04L25/38

    CPC分类号： H04L25/45

    摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

    摘要翻译： 用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。 异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO， 以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。 发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。 接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。 接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。 接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

    Method and apparatus for evaluating paths in an integrated circuit design
    7.
    发明授权
    Method and apparatus for evaluating paths in an integrated circuit design 有权
    用于评估集成电路设计中的路径的方法和装置

    公开(公告)号：US08079002B1

    公开(公告)日：2011-12-13

    申请号：US12344030

    申请日：2008-12-24

    申请人： Kuok-Khian Lo ,  Mark B. Roberts ,  Mohammed Fakhruddin ,  James Karp ,  Richard P. Burnley ,  Min-Hsing Chen

    发明人： Kuok-Khian Lo ,  Mark B. Roberts ,  Mohammed Fakhruddin ,  James Karp ,  Richard P. Burnley ,  Min-Hsing Chen

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5054

    摘要： An embodiment of the invention involves: providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit; identifying from the information in the database each conductive path of a selected type in the electrical circuit; extracting layout information from the database for each conductive path of the selected type; and calculating an electrical parameter for each conductive path of the selected type, as a function of the layout information obtained for that conductive path during the extracting. In addition, in a different configuration of the embodiment, a report can be generated containing information based on the electrical parameter calculated during the calculating for at least one of the conductive paths of the selected type.

    摘要翻译： 本发明的一个实施例涉及：提供包括表示电路集成电路内的布局的布局信息的数据库; 从数据库中的信息中识别电路中所选类型的每个导电路径; 从所述数据库中提取所选类型的每个导电路径的布局信息; 以及根据在提取期间为该导电路径获得的布局信息来计算所选类型的每个导电路径的电参数。 此外，在本实施例的不同配置中，可以生成包含基于在所选择的类型的至少一个导电路径的计算期间计算的电参数的信息的报告。

    Network media access controller embedded in an integrated circuit host interface
    8.
    发明授权
    Network media access controller embedded in an integrated circuit host interface 有权
    网络媒体访问控制器嵌入在集成电路主机接口中

    公开(公告)号：US07761643B1

    公开(公告)日：2010-07-20

    申请号：US12352225

    申请日：2009-01-12

    申请人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant ,  Stuart A. Nisbet ,  Gareth D. Edwards

    发明人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant ,  Stuart A. Nisbet ,  Gareth D. Edwards

    IPC分类号： G06F13/00 ,  G06F9/26 ,  H04L12/00

    CPC分类号： G06F15/7867

    摘要： A media access controller system embedded in an integrated circuit is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in an integrated circuit. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

    摘要翻译： 描述嵌入在集成电路中的媒体访问控制器系统。 用于与第一处理器进行通信的平台相关桥接器，其中所述平台相关桥接器与所述第一处理器的平台相关联，并且所述第一处理器嵌入在集成电路中。 主机接口电路耦合到与平台相关的桥接器，并且被配置为提供处理器接口，其中处理器接口用于经由平台相关桥接器与第一处理器通信，并且处理器接口具有平台独立总线，用于与第二 处理器。 至少一个媒体访问控制器耦合到主机接口电路。