公开(公告)号：US07035335B1

公开(公告)日：2006-04-25

申请号：US09854586

申请日：2001-05-11

申请人： Franco Iacobelli ,  Rajesh L. Motwani

发明人： Franco Iacobelli ,  Rajesh L. Motwani

IPC分类号： H04N7/12

CPC分类号： H04N21/434 ,  H04N21/42615

摘要： A transport stream parser is described. In particular, the transport stream parser is incorporated in a host system such as a set top box. The transport stream parser operates on a data stream having a plurality of packets that have MPEG data. Specifically, sometime after the transport stream is received by the host system, the transport stream is directed to the transport stream parser. The transport stream parser selects TS (transport stream) packets from the transport stream by searching for a first plurality of codes in a first portion of each TS packet. Moreover, the transport stream parser scans a data payload of the selected TS packets for a second plurality of codes to determine a plurality of parsing result codes. In addition, the transport stream parser adds a parsing result word having the parsing result codes to each TS packet.

摘要翻译： 描述了传输流解析器。 特别地，传输流解析器被并入诸如机顶盒的主机系统中。 传输流解析器对具有多个具有MPEG数据的分组的数据流进行操作。 具体来说，在主机系统接收到传输流之后的某个时刻，传输流被定向到传输流解析器。 传输流解析器通过搜索每个TS分组的第一部分中的第一多个代码来从传输流中选择TS（传输流）分组。 此外，传输流解析器扫描所选择的TS分组的数据有效载荷用于第二多个代码，以确定多个分析结果代码。 此外，传输流解析器将具有解析结果码的解析结果字添加到每个TS分组。

公开(公告)号：US5710939A

公开(公告)日：1998-01-20

申请号：US452350

申请日：1995-05-26

申请人： William Ballachino ,  James Andrew Colgan ,  Franco Iacobelli

发明人： William Ballachino ,  James Andrew Colgan ,  Franco Iacobelli

IPC分类号： G06F13/38 ,  G06F13/00

CPC分类号： G06F13/38 ,  G06F13/385

摘要： A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with data communication rates which are controlled by the host and slave state machines in accordance with the commands from the command registers. The communications of control signals by the host and slave state machines are responsive to their control signals with such responsiveness being controllable in accordance with the commands from the command registers. The communication of data from the FIFO to the peripheral device is halted by the host state machine in accordance with its commands from the command registers. The command registers include a status register for storing data from the peripheral device representing a number of status states of the peripheral device.

摘要翻译： 用于在计算机和外部外围设备之间提供并行数据接口的双向并行信号接口包括具有用于传送命令和数据的命令寄存器的接口电路，用于在计算机之间传送数据的先入先出（FIFO）存储器 外围设备，以及用于从命令寄存器接收命令的主机和从状态机，并且根据其控制FIFO和外围设备之间的数据通信，并向外部设备传送控制信号。 根据来自命令寄存器的命令由主机和从状态机控制的数据通信速率来实现FIFO和外围设备之间的数据通信。 主机和从状态机的控制信号的通信响应于它们的控制信号，其响应性根据来自命令寄存器的命令是可控的。 根据来自命令寄存器的命令，主机状态机停止从FIFO向外围设备的数据通信。 命令寄存器包括用于存储来自外围设备的数据的状态寄存器，其表示外围设备的状态数量。

公开(公告)号：US06919929B1

公开(公告)日：2005-07-19

申请号：US09823498

申请日：2001-03-29

申请人： Franco Iacobelli ,  Vikram Shrivastava

发明人： Franco Iacobelli ,  Vikram Shrivastava

IPC分类号： G09G5/12 ,  H04N5/04 ,  H04N5/45 ,  H04N5/46 ,  H04N9/64 ,  H04N9/74

CPC分类号： G09G5/12 ,  G09G2340/125 ,  G09G2352/00 ,  H04N5/04 ,  H04N5/45 ,  H04N5/46 ,  H04N9/641 ,  H04N21/42653 ,  H04N21/4305 ,  H04N21/4307 ,  H04N21/4316 ,  H04N21/44004 ,  H04N21/8146

摘要： A method and system for interfacing video and graphics data. Specifically, the present invention discloses a method and system for displaying video and graphics data of different formats and image frequencies onto the same display line. A master device that is continually streaming data of a first media type to a display at a certain image rate requests data from a source device one line at a time. The incoming line of data is sent to a FIFO buffer. A mixer associated with the master device then aligns the incoming data to the same format and image rate used for displaying the first media type. The incoming data is then displayed simultaneously on the same line with the data of the first media type. As viewed as an image, windows of video and/or graphics data are shown on a display.

摘要翻译： 一种用于接口视频和图形数据的方法和系统。 具体地，本发明公开了一种用于将不同格式和图像频率的视频和图形数据显示在同一显示行上的方法和系统。 以一定的图像速率连续地将数据传输到显示器的主设备一次一行地从源设备请求数据。 输入的数据行发送到FIFO缓冲区。 与主设备相关联的混音器然后将输入数据对准用于显示第一媒体类型的相同格式和图像速率。 然后，输入数据同时显示在与第一种媒体类型的数据相同的行上。 如图像所示，视频和/或图形数据的窗口显示在显示器上。

公开(公告)号：US5287458A

公开(公告)日：1994-02-15

申请号：US38713

申请日：1993-03-26

申请人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

发明人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

IPC分类号： H04L25/45 ,  G06F13/12

CPC分类号： H04L25/45

摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

摘要翻译： 用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。 异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO， 以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。 发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。 接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。 接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。 接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

公开(公告)号：US5241660A

公开(公告)日：1993-08-31

申请号：US703572

申请日：1991-05-17

申请人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

发明人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

IPC分类号： H04L25/45

CPC分类号： H04L25/45

摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

摘要翻译： 用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。 异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO， 以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。 发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。 接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。 接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。 接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

公开(公告)号：US4823312A

公开(公告)日：1989-04-18

申请号：US924797

申请日：1986-10-30

申请人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

发明人： Martin S. Michael ,  Prashant A. Kanhere ,  Richard P. Burnley ,  Franco Iacobelli ,  Ta-Wei Chien

IPC分类号： H04L25/45 ,  H04Q9/00 ,  G06F3/04 ,  H04L25/38

CPC分类号： H04L25/45

摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.

摘要翻译： 用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。 异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO， 以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。 发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。 接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。 接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。 接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。