公开(公告)号：US5710939A

公开(公告)日：1998-01-20

申请号：US452350

申请日：1995-05-26

申请人： William Ballachino ,  James Andrew Colgan ,  Franco Iacobelli

发明人： William Ballachino ,  James Andrew Colgan ,  Franco Iacobelli

IPC分类号： G06F13/38 ,  G06F13/00

CPC分类号： G06F13/38 ,  G06F13/385

摘要： A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with data communication rates which are controlled by the host and slave state machines in accordance with the commands from the command registers. The communications of control signals by the host and slave state machines are responsive to their control signals with such responsiveness being controllable in accordance with the commands from the command registers. The communication of data from the FIFO to the peripheral device is halted by the host state machine in accordance with its commands from the command registers. The command registers include a status register for storing data from the peripheral device representing a number of status states of the peripheral device.

摘要翻译： 用于在计算机和外部外围设备之间提供并行数据接口的双向并行信号接口包括具有用于传送命令和数据的命令寄存器的接口电路，用于在计算机之间传送数据的先入先出（FIFO）存储器 外围设备，以及用于从命令寄存器接收命令的主机和从状态机，并且根据其控制FIFO和外围设备之间的数据通信，并向外部设备传送控制信号。 根据来自命令寄存器的命令由主机和从状态机控制的数据通信速率来实现FIFO和外围设备之间的数据通信。 主机和从状态机的控制信号的通信响应于它们的控制信号，其响应性根据来自命令寄存器的命令是可控的。 根据来自命令寄存器的命令，主机状态机停止从FIFO向外围设备的数据通信。 命令寄存器包括用于存储来自外围设备的数据的状态寄存器，其表示外围设备的状态数量。