公开(公告)号：US20100001759A1

公开(公告)日：2010-01-07

申请号：US12419289

申请日：2009-04-06

申请人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

发明人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

IPC分类号： H03K19/173

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了一种可配置IC，其包括具有存储元件的可配置路由结构。 在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或向这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：US20080231318A1

公开(公告)日：2008-09-25

申请号：US11754299

申请日：2007-05-27

申请人： Herman Schmit ,  Randy Renfu Huang

发明人： Herman Schmit ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了一种可配置IC，其包括具有存储元件的可配置路由结构。 在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或向这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：US07514957B2

公开(公告)日：2009-04-07

申请号：US11754299

申请日：2007-05-27

申请人： Herman Schmit ,  Randy Renfu Huang

发明人： Herman Schmit ,  Randy Renfu Huang

IPC分类号： H03K19/173

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

公开(公告)号：US07259587B1

公开(公告)日：2007-08-21

申请号：US11081861

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

IPC分类号： H03K19/177 ,  H01L25/00

CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

公开(公告)号：US07839166B2

公开(公告)日：2010-11-23

申请号：US11856214

申请日：2007-09-17

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H03K19/17736 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00

摘要： Some embodiments provide an integrated circuit that includes several groups of circuits, each group of circuits includes a set of configurable logic circuits. The integrated circuit has at least one direct connection, without any intervening interconnect circuits, that connects an output of a configurable logic circuit in one group of circuits to another circuit in another group of circuits that does not neighbor the first group of circuits and that is not aligned with the first group of circuits. In some embodiments, the direct connection has intervening buffer circuits, but no other intervening circuits.

摘要翻译： 一些实施例提供了包括几组电路的集成电路，每组电路包括一组可配置的逻辑电路。 集成电路具有至少一个直接连接，没有任何中间互连电路，其将一组电路中的可配置逻辑电路的输出连接到不与第一组电路相邻的另一组电路中的另一电路， 不与第一组电路对齐。 在一些实施例中，直接连接具有中间缓冲电路，但没有其他中间电路。

公开(公告)号：US07576564B2

公开(公告)日：2009-08-18

申请号：US11868959

申请日：2007-10-08

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

摘要翻译： 一些实施例提供了一种可配置集成电路（“IC”），其包括以瓦片排列方式布置的多个可配置瓦片。 每个可配置的瓦片具有一组可配置逻辑电路和一组用于在可配置逻辑电路之间路由信号的可配置路由电路。 第一瓦片的至少第一路由电路具有与第二瓦片的第二电路的至少一个直接连接，第二瓦片不邻近第一瓦片，并且不与水平或垂直对准在瓦片布置中的第一瓦片。

公开(公告)号：US07295037B2

公开(公告)日：2007-11-13

申请号：US11082193

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

摘要翻译： 一些实施例提供了一种可配置集成电路（“IC”），其包括以瓦片排列方式布置的多个可配置瓦片。 每个可配置的瓦片具有一组可配置逻辑电路和一组用于在可配置逻辑电路之间路由信号的可配置路由电路。 第一瓦片的至少第一路由电路具有与第二瓦片的第二电路的至少一个直接连接，第二瓦片不邻近第一瓦片，并且不与水平或垂直对准在瓦片布置中的第一瓦片。

公开(公告)号：US08723549B2

公开(公告)日：2014-05-13

申请号：US13311544

申请日：2011-12-05

申请人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

发明人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了包括具有存储元件的可配置路由结构的可配置IC。 在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或向这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：US08093922B2

公开(公告)日：2012-01-10

申请号：US12419289

申请日：2009-04-06

申请人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

发明人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

IPC分类号： H03K19/173

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了一种可配置IC，其包括具有存储元件的可配置路由结构。 在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或向这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：US07518402B2

公开(公告)日：2009-04-14

申请号：US11775218

申请日：2007-07-09

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.