公开(公告)号：US20060046439A1

公开(公告)日：2006-03-02

申请号：US10527777

申请日：2003-08-21

Applicant: Ronald Dekker ,  Jan Baptist Van Der Putten ,  Ramon Havens

Inventor： Ronald Dekker ,  Jan Baptist Van Der Putten ,  Ramon Havens

IPC: H01L21/20 ,  H01L21/30 ,  H01L21/332 ,  H01L21/8234 ,  H01L21/50

CPC classification number: H01L29/66712 ,  H01L21/78 ,  H01L29/6631 ,  H01L29/781

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) in which, in a semiconductor body (1) with a temporary substrate (2), at least one semiconductor element (3) is formed which, on a side of the semiconductor body (1) opposite to the substrate (2), is provided with at least one connection region (4), and, on the said side, a dielectric (5) is formed and patterned to leave free the connection region (4), after which a metal layer (6) is deposited over the dielectric (5) so as to be in contact with the connection region (4), which metal layer (6) serves as an electric connection conductor of the connection region (4), after which the temporary substrate (2) is removed and the metal layer (6) also serves as a substrate of the device (10). According to the invention, before the metal layer (6) is deposited, there is formed, around the patterned part of the dielectric (5) and around the semiconductor element (3), an annular region (7) of a resin having a larger thickness than the dielectric (5), and the metal layer (6) is deposited within the rectangular annular region (7). In this way, an individual device (10) can readily be formed after the metal layer (6) has been deposited, preferably by pushing the device (10) out of the region (7). Preferably, a (different) photoresist is chosen for the dielectric (5) and the region (7). The invention also comprises a semiconductor device (10) obtained in this way.

Abstract translation: 本发明涉及一种制造半导体器件（10）的方法，其中在具有临时衬底（2）的半导体本体（1）中，形成至少一个半导体元件（3），其在半导体 本体（1）与基板（2）相对设置有至少一个连接区域（4），并且在所述侧面上形成有电介质（5）并图案化以使连接区域（4）免费， 之后将金属层（6）沉积在电介质（5）上以与连接区域（4）接触，该金属层（6）用作连接区域（4）的电连接导体， 之后移除临时衬底（2），金属层（6）也用作器件（10）的衬底。 根据本发明，在金属层（6）沉积之前，在电介质（5）的图案化部分周围形成围绕半导体元件（3）的环形区域（7），具有较大的 厚度比电介质（5）厚，并且金属层（6）沉积在矩形环形区域（7）内。 以这种方式，优选地，通过将​​装置（10）推出区域（7）之后，可以容易地在沉积金属层（6）之后形成单个装置（10）。 优选地，为电介质（5）和区域（7）选择（不同的）光致抗蚀剂。 本发明还包括以这种方式获得的半导体器件（10）。

公开(公告)号：US20060049481A1

公开(公告)日：2006-03-09

申请号：US10538109

申请日：2003-12-05

Applicant: Lukas Tiemeijer ,  Ramon Havens ,  Dominicus Leenaerts ,  Nenad Pavlovic ,  Hugo Veenstra ,  Edwin Van Der Heijden

Inventor： Lukas Tiemeijer ,  Ramon Havens ,  Dominicus Leenaerts ,  Nenad Pavlovic ,  Hugo Veenstra ,  Edwin Van Der Heijden

IPC: H01L29/00

CPC classification number: H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/367 ,  H01F2017/008 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a planar inductive component arranged over a substrate (103). The substrate in a first plane, a patterned ground shield (102), for shielding the winding (101) from the substrate (103). The winding (101) is at least substantially symmetrical plane. The patterned ground shield (102) comprises a plurality of electrical conductive first tracks (105) situated in a first ground shield plane in parallel with the first plane. The first tracks have an orientation perpendicular to the mirror plane (104). Without the patterned ground shield (102) the winding (101) is capacitively coupled to the substrate (103). The substrate resistance results in a degradation of the quality factor of the inductive component (100). The patterned ground shield (102) shields the winding (101) from the substrate (103), thereby eliminating the degrading effect of the substrate. To prevent a reduction in the effective self inductance of the planar inductive component loop currents have to be prevented in the patterned ground shield, while at the same time transfer of charges induced in the mirrored halves of the winding (100) have to be facilitated. This is achieved by the first tracks (105).

Abstract translation: 本发明涉及一种布置在基板（103）上的平面感应元件。 第一平面中的衬底，用于屏蔽绕组（101）与衬底（103）的图案化接地屏蔽（102）。 绕组（101）至少是基本对称的平面。 图案化接地屏蔽（102）包括位于与第一平面平行的第一接地屏蔽平面中的多个导电第一轨道（105）。 第一轨道具有垂直于镜面（104）的取向。 没有图案化的接地屏蔽（102），绕组（101）电容耦合到衬底（103）。 基板电阻导致电感元件（100）的品质因数的劣化。 图案化的接地屏蔽（102）将绕组（101）与衬底（103）屏蔽，从而消除衬底的劣化作用。 为了防止平面感应元件的有效自感的减小，必须在图案化的接地屏蔽中防止环路电流的流动，同时必须促进在绕组（100）的镜像半部中感应的电荷的传输。 这通过第一轨道（105）来实现。