Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer
    1.
    发明申请
    Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer 失效
    校准和解嵌方法,去嵌入设备和矢量网络分析仪

    公开(公告)号:US20060114004A1

    公开(公告)日:2006-06-01

    申请号:US11316497

    申请日:2005-12-21

    Inventor: Lukas Tiemeijer

    CPC classification number: G01R27/28 G01R35/005

    Abstract: Consistent with an example embodiment, there is a method for calibrating an N terminal microwave measurement network. The method comprising the measurement of network parameter values of a load device depends on the knowledge of the parasitic impedance of the load device. According to the example embodiment, the accuracy of the method is improved by at least approximately determining the parasitic impedances of the load device. This may be achieved by measuring network parameter values of an auxiliary open device, having substantially identical parasitic impedance as that of the load device. The accuracy is further increased by measuring network parameter values of an auxiliary short device, having substantially identical parasitic impedance as that of the load device. A similar principle can be used for de-embedding a device under test. A load device, an auxiliary open device and an auxiliary short device each having substantially identical parasitic impedances are disclosed.

    Abstract translation: 与示例性实施例一致,存在用于校准N端微波测量网络的方法。 包括对负载设备的网络参数值的测量的方法取决于负载设备的寄生阻抗的知识。 根据示例实施例,通过至少近似地确定负载装置的寄生阻抗来提高该方法的精度。 这可以通过测量具有与负载装置的寄生阻抗基本相同的寄生阻抗的辅助开路装置的网络参数值来实现。 通过测量具有与负载装置的寄生阻抗基本相同的寄生阻抗的辅助短路装置的网络参数值来进一步提高精度。 类似的原理可以用于解嵌入被测设备。 公开了一种负载装置,辅助开启装置和辅助短路装置,每个具有基本相同的寄生阻抗。

    High frequency transistor layout for low source drain capacitance
    2.
    发明申请
    High frequency transistor layout for low source drain capacitance 有权
    用于低源极漏极电容的高频晶体管布局

    公开(公告)号:US20070187780A1

    公开(公告)日:2007-08-16

    申请号:US11630855

    申请日:2005-06-22

    Inventor: Lukas Tiemeijer

    Abstract: An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimised for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.

    Abstract translation: RF场效应晶体管具有栅电极,梳状漏极和源电极,梳状漏极的指状物被布置成与源电极的指状物交错,源极和漏极具有多个层(110,120,130,140)。 交织的量在每层中是不同的,以便能够优化,特别是对于低寄生电容,而不会失去由多层提供的低电流密度的所有优点。 通过具有较短的手指,与栅极电极进一步层的交织减少。 通过交织的逐渐减少,交织的减少可以针对最小电容,交叉的更陡的减少或源极和漏极的最小横向电流密度进行优化。 这可以在更高的温度或更高的输入偏置电流下工作,同时仍然满足电迁移规则的要求。

    Planar inductive component and an integrated circuit comprising a planar inductive component
    3.
    发明申请
    Planar inductive component and an integrated circuit comprising a planar inductive component 审中-公开
    平面感应元件和包括平面感应元件的集成电路

    公开(公告)号:US20060049481A1

    公开(公告)日:2006-03-09

    申请号:US10538109

    申请日:2003-12-05

    Abstract: The invention relates to a planar inductive component arranged over a substrate (103). The substrate in a first plane, a patterned ground shield (102), for shielding the winding (101) from the substrate (103). The winding (101) is at least substantially symmetrical plane. The patterned ground shield (102) comprises a plurality of electrical conductive first tracks (105) situated in a first ground shield plane in parallel with the first plane. The first tracks have an orientation perpendicular to the mirror plane (104). Without the patterned ground shield (102) the winding (101) is capacitively coupled to the substrate (103). The substrate resistance results in a degradation of the quality factor of the inductive component (100). The patterned ground shield (102) shields the winding (101) from the substrate (103), thereby eliminating the degrading effect of the substrate. To prevent a reduction in the effective self inductance of the planar inductive component loop currents have to be prevented in the patterned ground shield, while at the same time transfer of charges induced in the mirrored halves of the winding (100) have to be facilitated. This is achieved by the first tracks (105).

    Abstract translation: 本发明涉及一种布置在基板(103)上的平面感应元件。 第一平面中的衬底,用于屏蔽绕组(101)与衬底(103)的图案化接地屏蔽(102)。 绕组(101)至少是基本对称的平面。 图案化接地屏蔽(102)包括位于与第一平面平行的第一接地屏蔽平面中的多个导电第一轨道(105)。 第一轨道具有垂直于镜面(104)的取向。 没有图案化的接地屏蔽(102),绕组(101)电容耦合到衬底(103)。 基板电阻导致电感元件(100)的品质因数的劣化。 图案化的接地屏蔽(102)将绕组(101)与衬底(103)屏蔽,从而消除衬底的劣化作用。 为了防止平面感应元件的有效自感的减小,必须在图案化的接地屏蔽中防止环路电流的流动,同时必须促进在绕组(100)的镜像半部中感应的电荷的传输。 这通过第一轨道(105)来实现。

    Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer
    4.
    发明申请
    Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer 失效
    校准和解嵌方法,去嵌入设备和矢量网络分析仪

    公开(公告)号:US20050179444A1

    公开(公告)日:2005-08-18

    申请号:US10514327

    申请日:2003-05-08

    Inventor: Lukas Tiemeijer

    CPC classification number: G01R27/28 G01R35/005

    Abstract: The accuracy of a method for calibrating an N terminal microwave measurement network (10), the method comprising the measurement of network parameter values of a load device (43), depends on the knowledge of the parasitic impedance of the load device (43). According to the invention, the accuracy of the method is improved by at least approximately determining the parasitic impedances of the load device (43). In one embodiment this is achieved by measuring network parameter values of an auxiliary open device (44), having a substantially identical parasitic impedance as the load device (43). The accuracy is further increased by measuring network parameter values of an auxiliary short device (45), having a substantially identical parasitic impedance as the load device (43). A similar principle can be used for de-embedding a device under test. A load device (43), an auxiliary open device (44) and an auxiliary short device (45) having substantially identical parasitic impedances are disclosed.

    Abstract translation: 用于校准N端微波测量网络(10)的方法的准确性,包括对负载设备(43)的网络参数值的测量的方法取决于负载设备(43)的寄生阻抗的知识。 根据本发明,通过至少近似地确定负载装置(43)的寄生阻抗来提高该方法的精度。 在一个实施例中,这通过测量具有与负载装置(43)基本上相同的寄生阻抗的辅助开路装置(44)的网络参数值来实现。 通过测量与负载装置(43)具有基本上相同的寄生阻抗的辅助短路装置(45)的网络参数值来进一步提高精度。 类似的原理可以用于解嵌入被测设备。 公开了具有基本上相同的寄生阻抗的负载装置(43),辅助开启装置(44)和辅助短路装置(45)。

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