公开(公告)号：US08368578B2

公开(公告)日：2013-02-05

申请号：US13113884

申请日：2011-05-23

申请人： Pieter Harpe

发明人： Pieter Harpe

IPC分类号： H03M1/12

CPC分类号： H03M1/56

摘要： The present invention is related to an analog to digital converter circuit. The circuit comprises at least one input node for applying an analog input voltage signal (Vin), means for sampling said analog input voltage signal, a first array of capacitors arranged for receiving the sampled analog input voltage signal, a digital delay line connected to the first array of capacitors and arranged for being enabled by a clock generator and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator arranged for comparing a converted signal with a reference voltage (Vref), said converted signal being a version of said sampled analog input voltage converted according to said staircase or slope function, and for generating a stop signal based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.

摘要翻译： 本发明涉及一种模数转换器电路。 该电路包括用于施加模拟输入电压信号（Vin）的至少一个输入节点，用于对所述模拟输入电压信号进行采样的装置，用于接收采样模拟输入电压信号的第一阵列电容器，连接到所述模拟输入电压信号的数字延迟线 第一阵列电容器，并被布置成由时钟发生器使能，并且通过第一电容器阵列产生阶梯或斜率函数，考虑到采样的模拟输入电压信号;比较器，被布置为将转换的信号与参考值进行比较 电压（Vref），所述转换信号是根据所述阶梯或斜率函数转换的所述采样的模拟输入电压的版本，并且用于基于比较结果产生停止信号从而锁存数字延迟线，从而获取数字代码。

公开(公告)号：US20110285568A1

公开(公告)日：2011-11-24

申请号：US13113884

申请日：2011-05-23

申请人： Pieter Harpe

发明人： Pieter Harpe

IPC分类号： H03M1/34

CPC分类号： H03M1/56

摘要： The present invention is related to an analog to digital converter circuit. The circuit comprises at least one input node for applying an analog input voltage signal (Vin), means for sampling said analog input voltage signal, a first array of capacitors arranged for receiving the sampled analog input voltage signal, a digital delay line connected to the first array of capacitors and arranged for being enabled by a clock generator and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator arranged for comparing a converted signal with a reference voltage (Vref), said converted signal being a version of said sampled analog input voltage converted according to said staircase or slope function, and for generating a stop signal based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.

摘要翻译： 本发明涉及一种模数转换器电路。 该电路包括用于施加模拟输入电压信号（Vin）的至少一个输入节点，用于对所述模拟输入电压信号进行采样的装置，用于接收采样模拟输入电压信号的第一阵列电容器，连接到所述模拟输入电压信号的数字延迟线 第一阵列电容器，并被布置成由时钟发生器使能，并且通过第一电容器阵列产生阶梯或斜率函数，考虑到采样的模拟输入电压信号;比较器，被布置为将转换的信号与参考值进行比较 电压（Vref），所述转换信号是根据所述阶梯或斜率函数转换的所述采样的模拟输入电压的版本，并且用于基于比较结果产生停止信号从而锁存数字延迟线，从而获取数字代码。

公开(公告)号：US20070290906A1

公开(公告)日：2007-12-20

申请号：US10565929

申请日：2004-07-15

申请人： Derk Reefman ,  Pieter Harpe ,  Erwin Janssen

发明人： Derk Reefman ,  Pieter Harpe ,  Erwin Janssen

IPC分类号： H03M3/02

CPC分类号： H03M7/3011 ,  H03M7/3028

摘要： Improved sigma-delta modulator (SDM) for 1-bit digital audio noise shaping. It is the object to produce a bit stream that is compatible with the Scarlet Book specification (Super Audio CD standard, SACD) and that achieves a higher lossless compression ratio when compressed and decompressed according to the standard. This goal is achieved by using a trellis-based SDM and/or a prediction filter within the SDM that is similar or identical to the prediction filter in the encoder. The trellis SDM is designed to produce a predicted signal from a range of candidate signals that is as close to the input signal as possible.

摘要翻译： 改进的Σ-Δ调制器（SDM）用于1位数字音频噪声整形。 产生与Scarlet Book规范（Super Audio CD标准，SACD）兼容的比特流的目的是在根据标准进行压缩和解压缩时实现更高的无损压缩比。 该目标通过使用与编码器中的预测滤波器相似或相同的SDM内的基于网格的SDM和/或预测滤波器来实现。 网格SDM被设计为从尽可能接近输入信号的候选信号的范围产生预测信号。

公开(公告)号：US08134487B2

公开(公告)日：2012-03-13

申请号：US12878677

申请日：2010-09-09

申请人： Pieter Harpe

发明人： Pieter Harpe

IPC分类号： H03M1/34

CPC分类号： H03M1/125 ,  H03M1/462

摘要： An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output.

摘要翻译： 提出了一种用于将模拟输入信号转换为数字输出的异步模数转换器。 根据实施例，模数转换器包括可操作以接收具有时钟周期的外部时钟信号的时钟输入，可操作以将模拟输入信号与参考信号进行比较的比较器，可操作以产生参考的数模转换器 对应于逐次逼近寄存器的状态的信号，以及连接到比较器和数模转换器的控制块。 控制块可操作以根据逐次逼近算法产生和接收控制信号序列，以执行多个比较，并且更新逐次逼近寄存器的状态，从而生成数字输出。

公开(公告)号：US20110057823A1

公开(公告)日：2011-03-10

申请号：US12878677

申请日：2010-09-09

申请人： Pieter Harpe

发明人： Pieter Harpe

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/125 ,  H03M1/462

摘要： An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output.

摘要翻译： 提出了一种用于将模拟输入信号转换为数字输出的异步模数转换器。 根据实施例，模数转换器包括可操作以接收具有时钟周期的外部时钟信号的时钟输入，可操作以将模拟输入信号与参考信号进行比较的比较器，可操作以产生参考的数模转换器 对应于逐次逼近寄存器的状态的信号，以及连接到比较器和数模转换器的控制块。 控制块可操作以根据逐次逼近算法产生和接收控制信号序列，以执行多个比较，并且更新逐次逼近寄存器的状态，从而生成数字输出。