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17 条记录 (耗时 0.017 秒)

    Method of making a polymer device
    2.
    发明授权
    Method of making a polymer device 有权
    制造聚合物装置的方法

    公开(公告)号：US07718549B2

    公开(公告)日：2010-05-18

    申请号：US10566984

    申请日：2004-08-11

    申请人： Lay-lay Chua ,  Peter Kian-Hoon Ho ,  Henning Sirringhaus ,  Richard Henry Friend

    发明人： Lay-lay Chua ,  Peter Kian-Hoon Ho ,  Henning Sirringhaus ,  Richard Henry Friend

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L51/0003 ,  B82Y10/00 ,  B82Y30/00 ,  H01L51/0012 ,  H01L51/0028

    摘要： A method of making a transistor having first and second electrodes, a semiconductive layer, and a dielectric layer; said semiconductive layer comprising a semiconductive polymer and said dielectric layer comprising an insulating polymer; characterised in that said method comprises the steps of: (i) depositing on the first electrode a layer of a solution containing material for forming the semiconductive layer and material for forming the dielectric layer; and (ii) optionally curing the layer deposited in step (i); wherein, in step (i), the solvent drying time, the temperature of the first electrode and the weight ratio, of (material for forming the dielectric layer): (material for forming the semiconductive layer) in the solution are selected so that the material for forming the semiconductive layer and the material for forming the dielectric layer phase separate by self-organisation to form an interface between the material for forming the semiconductive layer and the material for forming the dielectric layer.

    摘要翻译： 一种制造具有第一和第二电极的晶体管的方法，半导体层和电介质层; 所述半导体层包括半导体聚合物，所述介电层包含绝缘聚合物; 其特征在于所述方法包括以下步骤：（i）在第一电极上沉积含有用于形成半导体层的材料的溶液层和用于形成介电层的材料; 和（ii）任选地固化在步骤（i）中沉积的层; 其中，在步骤（i）中，选择溶液中的（用于形成介电层的材料）的溶剂干燥时间，第一电极的温度和重量比：（用于形成半导体层的材料），使得 用于形成半导体层的材料和用于形成电介质层相的材料通过自组织分离，以在用于形成半导体层的材料和用于形成电介质层的材料之间形成界面。

    Dual-Gate Transistors
    3.
    发明申请
    Dual-Gate Transistors 审中-公开
    双栅晶体管

    公开(公告)号：US20080283825A1

    公开(公告)日：2008-11-20

    申请号：US11547269

    申请日：2005-04-05

    申请人： Lay-Lay Chua ,  Peter Kian-Hoon Ho ,  Richard Henry Friend

    发明人： Lay-Lay Chua ,  Peter Kian-Hoon Ho ,  Richard Henry Friend

    IPC分类号： H01L51/05

    CPC分类号： H01L51/0508 ,  H01L27/283 ,  H01L51/0512 ,  H01L51/0554

    摘要： A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode and a second dielectric region located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode.

    摘要翻译： 一种场效应晶体管器件，包括：源电极; 漏电极; 半导体区域，包括有机半导体材料，并且限定所述源电极和所述漏电极之间的所述器件的沟道; 第一栅极结构，包括位于第一栅极电极和半导体区域之间的第一栅极电极和第一电介质区域; 以及第二栅极结构，其包括位于所述第二栅极电极和所述半导体区域之间的第二栅电极和第二电介质区域; 由此沟道中的半导体区域的电导可以受单独施加的电位或第一栅极电极和第二栅极电极的影响。

    Forming patterned thin film metal layers
    5.
    发明授权
    Forming patterned thin film metal layers 有权
    形成图案化的薄膜金属层

    公开(公告)号：US06770549B2

    公开(公告)日：2004-08-03

    申请号：US10141362

    申请日：2002-05-08

    申请人： Zhenan Bao ,  Peter Kian-Hoon Ho ,  Takao Someya

    发明人： Zhenan Bao ,  Peter Kian-Hoon Ho ,  Takao Someya

    IPC分类号： H01L2120

    CPC分类号： H01L21/76838 ,  H01L21/288 ,  H01L51/0021 ,  H01L51/0024 ,  H01L51/0097 ,  H01L51/0512

    摘要： The specification describes a pattern transfer technique for forming patterns of thin films of high resolution over large areas. It involves forming a pattern layer on a transfer substrate, patterning the pattern layer while on the transfer substrate, then contacting the transfer substrate with the receiving substrate. The surface of the receiving substrate is treated to activate the surface thereby improving adhesion of the transfer pattern to the receiving substrate. The activation treatment involves forming a layer of metal particles on the surface of the receiving substrate. The pattern layer is preferably of the same metal, or a similar metal or alloy, and is transferred from the transfer substrate to the receiving substrate by metallurgical bonding. The method of the invention is particularly useful for printing metal conductor patterns (metalization), and device features, on flexible polymer substrates in, for example, thin film transistor (TFT) technology.

    摘要翻译： 本说明书描述了用于在大面积上形成高分辨率薄膜图案的图案转印技术。 它涉及在转移基板上形成图案层，在转印衬底上图案化图案层，然后使转印衬底与接收衬底接触。 处理接收基板的表面以激活表面，从而改善转印图案对接收基板的粘附。 活化处理包括在接收基材的表面上形成一层金属颗粒。 图案层优选为相同的金属或类似的金属或合金，并且通过冶金结合从转印基板转移到接收基板。本发明的方法特别适用于印刷金属导体图案（金属化）和 在诸如薄膜晶体管（TFT）技术的柔性聚合物基板上的器件特征。

    DUAL-GATE TRANSISTORS
    9.
    发明申请
    DUAL-GATE TRANSISTORS 审中-公开
    双门极晶体管

    公开(公告)号：US20120154025A1

    公开(公告)日：2012-06-21

    申请号：US13345038

    申请日：2012-01-06

    申请人： Lay-Lay CHUA ,  Peter Kian-Hoon Ho ,  Richard Henry Friend

    发明人： Lay-Lay CHUA ,  Peter Kian-Hoon Ho ,  Richard Henry Friend

    IPC分类号： G05F3/02

    CPC分类号： H01L51/0508 ,  H01L27/283 ,  H01L51/0512 ,  H01L51/0554

    摘要： A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode and a second dielectric region located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode.

    摘要翻译： 一种场效应晶体管器件，包括：源电极; 漏电极; 半导体区域，包括有机半导体材料，并且限定所述源电极和所述漏电极之间的所述器件的沟道; 第一栅极结构，包括位于第一栅极电极和半导体区域之间的第一栅极电极和第一电介质区域; 以及第二栅极结构，包括位于所述第二栅极电极和所述半导体区域之间的第二栅电极和第二电介质区域; 由此沟道中的半导体区域的电导可以受单独施加的电位或第一栅极电极和第二栅极电极的影响。