-
公开(公告)号：US06593660B2
公开(公告)日：2003-07-15
申请号：US09866937
申请日：2001-05-29
Applicant: Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
Inventor： Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
IPC: H01L2348
CPC classification number: H01L21/3185 , H01L21/0445 , H01L21/76801 , H01L21/76807 , H01L21/76834
Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
Abstract translation: 本发明利用还原等离子体处理步骤来增强后续沉积的无机阻挡膜对铜线的粘附，或通过存在于诸如双镶嵌结构的半导体互连结构中。 在所述铜线或通孔与无机阻挡膜之间形成包括作为必需元素的Cu，Si和O的材料层的互连结构。
-
Patent Agency Ranking
公开(公告)号：US07388224B2
公开(公告)日：2008-06-17
申请号：US11502196
申请日：2006-08-10
Applicant: Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
Inventor： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC: H01L23/58
CPC classification number: H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
Abstract translation: 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。
-
公开(公告)号：US07098054B2
公开(公告)日：2006-08-29
申请号：US10783462
申请日：2004-02-20
Applicant: Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
Inventor： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC: H01L21/66
CPC classification number: H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
-
公开(公告)号：US06261951B1
公开(公告)日：2001-07-17
申请号：US09472346
申请日：1999-12-27
Applicant: Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
Inventor： Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
IPC: H01L214763
CPC classification number: H01L21/3185 , H01L21/0445 , H01L21/76801 , H01L21/76807 , H01L21/76834
Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
-
公开(公告)号：US09287186B2
公开(公告)日：2016-03-15
申请号：US12128260
申请日：2008-05-28
Applicant: Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
Inventor： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
CPC classification number: H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
-
公开(公告)号：US20080224135A1
公开(公告)日：2008-09-18
申请号：US12128260
申请日：2008-05-28
Applicant: Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
Inventor： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
IPC: H01L23/58
CPC classification number: H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
Abstract translation: 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。
-
-
-
-
-
Search Results
6
records
(took 0.018 seconds)
