公开(公告)号：US4994962A

公开(公告)日：1991-02-19

申请号：US264260

申请日：1988-10-28

申请人： Paul Mageau ,  John S. Yates

发明人： Paul Mageau ,  John S. Yates

IPC分类号： G06F12/04 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A method and apparatus for selectively filling a cache memory with a variable number of data words in response to the size and type of data transfer requested by the processor associated with the cache. According to the present invention a cache fill of either 16 or 64 bytes are provided. If there is a cache miss and an 8 byte word data transfer as requested, the larger fill is provided, similarly, if the 8 byte word data transfer is not requested, the shorter block of data is provided, resulting in enhanced performance over a fixed length cache fill.

公开(公告)号：US5163142A

公开(公告)日：1992-11-10

申请号：US544049

申请日：1990-06-22

申请人： Paul Mageau

发明人： Paul Mageau

IPC分类号： G06F12/08

CPC分类号： G06F12/0855

摘要： An efficient cache write technique useful in digital computer systems wherein it is desired to achieve single cycle cache write access even when the processor cycle time does not allow sufficient time for the cache control to check the cache "tag" for validity and to reflect those results to the processor within the same processor cycle. The novel method and apparatus comprising a two-stage cache access pipeline which embellishes a simple "write-thru with write-allocate" cache write policy.

摘要翻译： 一种在数字计算机系统中有用的有效的高速缓存写入技术，其中即使在处理器循环时间不足以允许高速缓存控制的时间来检查高速缓存“标签”以获得有效性并且反映这些结果时，希望实现单周期高速缓存写入访问 在同一处理器周期内处理器。 该新颖的方法和装置包括一个两级高速缓存访​​问流水线，其具有简单的“写入 - 分配”高速缓存写入策略。