公开(公告)号：US07000065B2

公开(公告)日：2006-02-14

申请号：US10038960

申请日：2002-01-02

Applicant: Jeffrey R. Wilcox ,  Noam Yosef

Inventor： Jeffrey R. Wilcox ,  Noam Yosef

IPC: G06F12/00

CPC classification number: G06F13/16 ,  G06F1/3225 ,  G06F1/3253 ,  G06F13/1668 ,  Y02D10/151

Abstract: A method and apparatus for selectively disabling sense amplifiers to reduce power consumption in a memory bus interface are disclosed. The method includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence or end of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus. According to some embodiments, the disabling of the amplification may be synchronized to an edge of a delayed data strobe signal. In some embodiments, signals associated with a double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device may be communicated over the memory bus.

Abstract translation: 公开了一种用于选择性地禁用读出放大器以减少存储器总线接口中的功耗的方法和装置。 该方法包括从存储器总线接口放大数据信号。 放大的数据信号被采样，并且响应于在存储器总线上发生的预定操作的不存在或结束而选择性地禁止放大器。 在本发明的一些实施例中，响应于存储器总线上的预定操作的开始，可以选择性地启用放大。 根据一些实施例，放大禁用可以与延迟的数据选通信号的边沿同步。 在一些实施例中，可以通过存储器总线传送与双倍数据速率（“DDR”）同步动态随机存取存储器（“SDRAM”）设备相关联的信号。

公开(公告)号：US10102157B2

公开(公告)日：2018-10-16

申请号：US13447583

申请日：2012-04-16

Applicant: Jeffrey R. Wilcox ,  Noam Yosef

Inventor： Jeffrey R. Wilcox ,  Noam Yosef

IPC: G06F13/16 ,  G06F1/32

Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

公开(公告)号：US20130103867A1

公开(公告)日：2013-04-25

申请号：US13447583

申请日：2012-04-16

Applicant: Jeffrey R. Wilcox ,  Noam Yosef

Inventor： Jeffrey R. Wilcox ,  Noam Yosef

IPC: G06F13/16

CPC classification number: G06F13/16 ,  G06F1/3225 ,  G06F1/3253 ,  G06F13/1668 ,  Y02D10/151

Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

Abstract translation: 一种技术包括从存储器总线接口放大数据信号。 放大的数据信号被采样，并且响应于在存储器总线上不存在预定的操作而选择性地禁用放大器。 在本发明的一些实施例中，响应于存储器总线上的预定操作的开始，可以选择性地启用放大。

公开(公告)号：US08176240B2

公开(公告)日：2012-05-08

申请号：US11354304

申请日：2006-02-14

Applicant: Jeffrey R. Wilcox ,  Noam Yosef

Inventor： Jeffrey R. Wilcox ,  Noam Yosef

IPC: G06F12/00

CPC classification number: G06F13/16 ,  G06F1/3225 ,  G06F1/3253 ,  G06F13/1668 ,  Y02D10/151

Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

Abstract translation: 一种技术包括从存储器总线接口放大数据信号。 放大的数据信号被采样，并且响应于在存储器总线上不存在预定的操作而选择性地禁用放大器。 在本发明的一些实施例中，响应于存储器总线上的预定操作的开始，可以选择性地启用放大。

公开(公告)号：US06970010B2

公开(公告)日：2005-11-29

申请号：US10643802

申请日：2003-08-18

Applicant: Jeffrey R. Wilcox ,  Noam Yosef ,  Marcelo Yuffe

Inventor： Jeffrey R. Wilcox ,  Noam Yosef ,  Marcelo Yuffe

IPC: H03K19/00 ,  H04L25/02 ,  H03K19/0175

CPC classification number: H04L25/0282 ,  H03K19/0013 ,  H04L25/0298

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract translation: 描述了一种涉及通过线路驱动第一电流和终端电阻的方法，使得线路上的逻辑值从第一逻辑值改变为第二逻辑值。 该方法还包括通过驱动通过线路的第二电流以及第二电流小于第一电流的终端电阻来在线路上保持第二逻辑值。 描述了一种装置，其包括驱动通过线路的第一电流的驱动器和终端电阻，使得线路上的逻辑值从第一逻辑值改变为第二逻辑值。 驱动器通过驱动第二个电流通过线路和终端电阻，在线路上保持第二个逻辑值。 第二电流小于所述第一电流。

公开(公告)号：US06633178B2

公开(公告)日：2003-10-14

申请号：US09968259

申请日：2001-09-28

Applicant: Jeffrey R. Wilcox ,  Noam Yosef ,  Marcelo Yuffe

Inventor： Jeffrey R. Wilcox ,  Noam Yosef ,  Marcelo Yuffe

IPC: H03K190175

CPC classification number: H04L25/0282 ,  H03K19/0013 ,  H04L25/0298

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract translation: 描述了一种涉及通过线路驱动第一电流和终端电阻的方法，使得线路上的逻辑值从第一逻辑值改变为第二逻辑值。 该方法还包括通过驱动通过线路的第二电流以及第二电流小于第一电流的终端电阻来在线路上保持第二逻辑值。 描述了一种装置，其包括驱动通过线路的第一电流的驱动器和终端电阻，使得线路上的逻辑值从第一逻辑值改变为第二逻辑值。 驱动器通过驱动第二个电流通过线路和终端电阻，在线路上保持第二个逻辑值。 第二个电流小于第一个电流。

公开(公告)号：US06747475B2

公开(公告)日：2004-06-08

申请号：US10024119

申请日：2001-12-17

Applicant: Marcelo Yuffe ,  Zelig Wayner ,  Noam Yosef

Inventor： Marcelo Yuffe ,  Zelig Wayner ,  Noam Yosef

IPC: H03K19003

CPC classification number: H04L25/028 ,  G06F13/4072 ,  G06F13/4086 ,  H04L25/0278 ,  H04L25/0292

Abstract: A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.

Abstract translation: 用于在总线上驱动和接收信号的电路包括上拉开关和下拉开关。 上拉开关具有与总线线路的特性阻抗匹配的阻抗。 下拉开关的阻抗约为总线特性阻抗的一半。 当电路在总线上接收信号或驱动逻辑高电平信号时，使能上拉开关，使总线电压上拉，同时禁用下拉开关以防止下拉开关 从下拉母线电压。 当电路驱动总线上的逻辑低电平信号时，下拉开关被使能，使得总线电压被拉低，而上拉开关被禁止，以防止上拉开关向上拉 总线电压。

公开(公告)号：US20060190751A1

公开(公告)日：2006-08-24

申请号：US11354304

申请日：2006-02-14

Applicant: Jeffrey Wilcox ,  Noam Yosef

Inventor： Jeffrey Wilcox ,  Noam Yosef

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F13/16 ,  G06F1/3225 ,  G06F1/3253 ,  G06F13/1668 ,  Y02D10/151

Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

Abstract translation: 一种技术包括从存储器总线接口放大数据信号。 放大的数据信号被采样，并且响应于在存储器总线上不存在预定的操作而选择性地禁用放大器。 在本发明的一些实施例中，响应于存储器总线上的预定操作的开始，可以选择性地启用放大。