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1.发明授权Systems, circuits and methods for filtering signals to compensate for channel effects 有权用于滤波信号以补偿信道效应的系统，电路和方法公开(公告)号：US08948331B2
公开(公告)日：2015-02-03
申请号：US13931099
申请日：2013-06-28
发明人： Halil Cirit , Stefanos Sidiropoulos
IPC分类号： H04L7/00 , H04L25/03 , H04B10/2507
CPC分类号： H04B10/2507 , H04L25/03063 , H04L25/0307 , H04L25/03076
摘要： Embodiments of circuits and methods are described for decreasing transmitter waveform dispersion penalty (TWDP) in a transmitter. A data stream is received for transmission across a channel and a main data signal is generated from the data stream. At least two cursor signals are generated where each of the at least two cursor signals are shifted at least a portion of a clock period from the main data signal. The at least two cursor signals are subtracted from the main data signal to generate an output data signal with improved TWDP. Other embodiments include generating a main data signal, a pre-cursor signal shifted on previous clock cycle relative to the main data signal, and a post-cursor signal Shifted one subsequent clock cycle relative to the main data signal. The pre and post cursor signals are subtracted from the main data signal to generate an output data signal.
摘要翻译： 描述了用于降低发射机中的发射机波形色散惩罚（TWDP）的电路和方法的实施例。 接收数据流以通过信道传输，并从数据流生成主数据信号。 产生至少两个光标信号，其中至少两个光标信号中的每一个从主数据信号中移位到时钟周期的至少一部分。 从主数据信号中减去至少两个光标信号，以产生具有改进的TWDP的输出数据信号。 其他实施例包括产生主数据信号，相对于主数据信号在先前时钟周期上移位的前置光标信号，以及相对于主数据信号移位一个后续时钟周期的后光标信号。 从主数据信号中减去前后游标信号，生成输出数据信号。
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2.发明申请INTEGRATED CIRCUIT DEVICES, SYSTEMS AND METHODS HAVING AUTOMATIC CONFIGURABLE MAPPING OF INPUT AND/OR OUTPUT DATA CONNECTIONS 有权具有输入和/或输出数据连接的自动配置映射的集成电路设备，系统和方法公开(公告)号：US20140244868A1
公开(公告)日：2014-08-28
申请号：US14069590
申请日：2013-11-01
发明人： Whay Sing Lee
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F11/28 , G06F13/4291
摘要： Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.
摘要翻译： 公开了具有接收端口的集成电路装置，其具有可自动配置的映射电路，以改变在接收数据连接上接收的数据的逻辑映射。 自动配置可以基于包含在接收数据集中的数据值。 还描述了相应的系统和方法。
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3.发明授权Methods and circuits for limiting bit line leakage current in a content addressable memory (CAM) device 有权用于限制内容可寻址存储器（CAM）设备中的位线泄漏电流的方法和电路公开(公告)号：US08724359B2
公开(公告)日：2014-05-13
申请号：US13729771
申请日：2012-12-28
发明人： Martin Fabry
IPC分类号： G11C15/00
摘要： A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of, an access operation.
摘要翻译： 内容可寻址存储器（CAM）设备可以包括多个位线。 一个或多个位线可以连接到相应列中的CAM单元的存储电路。 每个CAM单元可以包括比较电路，其比较存储的值一个或多个比较数据值。 隔离电路可以具有连接在位线和预充电电压节点之间的可控阻抗路径，并且可以通过在控制节点处施加电位来控制。 控制电路可以耦合到控制节点，并且可以在进入操作的至少一部分之前和之后的隔离电路从高阻抗状态切换到低阻抗状态。
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4.发明授权System and method for conditionally sending a request for data to a home node 失效用于有条件地向家庭节点发送数据请求的系统和方法公开(公告)号：US08713255B2
公开(公告)日：2014-04-29
申请号：US13875016
申请日：2013-05-01
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0831 , G06F12/084 , G06F2212/1024 , G06F2212/2542
摘要： A system, method, and computer program product are provided for conditionally sending a request for data to a home node. In operation, a first request for data is sent to a first cache of a node. Additionally, if the data does not exist in the first cache, a second request for the data is sent to a second cache of the node. Furthermore, a third request for the data is conditionally sent to a home node.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于有条件地向家庭节点发送数据请求。 在操作中，向数据的第一高速缓存发送第一个数据请求。 此外，如果数据不存在于第一高速缓存中，则将数据的第二请求发送到节点的第二高速缓存。 此外，对数据的第三请求有条件地发送到家庭节点。
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5.发明申请METHODS AND CIRCUITS FOR LIMITING BIT LINE LEAKAGE CURRENT IN A CONTENT ADDRESSABLE MEMORY (CAM) DEVICE 有权用于限制内部可寻址存储器（CAM）器件中的位线泄漏电流的方法和电路公开(公告)号：US20130121053A1
公开(公告)日：2013-05-16
申请号：US13729771
申请日：2012-12-28
发明人： Martin FABRY
摘要： A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of an access operation.
摘要翻译： 内容可寻址存储器（CAM）设备可以包括多个位线。 一个或多个位线可以连接到相应列中的CAM单元的存储电路。 每个CAM单元可以包括比较电路，其比较存储的值一个或多个比较数据值。 隔离电路可以具有连接在位线和预充电电压节点之间的可控阻抗路径，并且可以通过在控制节点处施加电位来控制。 控制电路可以耦合到控制节点，并且可以在进入操作的至少一部分的持续时间之前将隔离电路从高阻抗状态切换到低阻抗状态。
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6.发明申请Low-Power and Low-Cost Adaptive Self-Linearization System with Fast Convergence 有权具有快速收敛性的低功耗和低成本自适应自我线性化系统公开(公告)号：US20130089169A1
公开(公告)日：2013-04-11
申请号：US13689294
申请日：2012-11-29
发明人： Roy G. Batruni
IPC分类号： H04B1/10
CPC分类号： H04B1/10 , G01R31/31709 , H03H21/0012 , H03H2021/0041 , H03H2021/0083 , H03M1/1042 , H03M1/12
摘要： A signal processing method includes inputting a digital signal, providing a plurality of coefficients; and determining an output. The output is approximately equal to an aggregate of a plurality of linear reference components, and each of the linear reference components is approximately equal to an aggregate of a corresponding set of digital signal samples that is scaled by the plurality of coefficients.
摘要翻译： 信号处理方法包括输入数字信号，提供多个系数; 并确定输出。 输出近似等于多个线性参考分量的总和，并且每个线性参考分量近似等于由多个系数缩放的对应的一组数字信号样本的总和。
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公开(公告)号：US09123417B1
公开(公告)日：2015-09-01
申请号：US14106237
申请日：2013-12-13
发明人： Dimitri Argyres
摘要： A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.
摘要翻译： 公开了可以选择性地配置为存储基2数据字或基3数据字的CAM单元。 当配置为存储基3数据字时，四元CAM单元将表示基3比较值的3个比较位与存储在CAM单元中的基3数据值进行比较。 在这样的CAM单元中存储基3数据字增加了相关CAM阵列的数据存储密度。
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公开(公告)号：US20150074442A1
公开(公告)日：2015-03-12
申请号：US14024063
申请日：2013-09-11
发明人： Ahmed SHAHID , Kaushik Kuila , David T. Hass
IPC分类号： G06F1/00
CPC分类号： G06F1/00 , G06F1/12 , G06F1/14 , H04J3/0667 , H04J3/0685
摘要： A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.
摘要翻译： 提供了一种用于减少与多核，多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心，多个用于网络通信的网络接口，以及定时器电路，用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。
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9.发明申请METHOD AND APPARATUS FOR HANDLING DATA FLOW IN A MULTI-CHIP ENVIRONMENT USING AN INTERCHIP INTERFACE 有权在使用交互接口的多芯片环境中处理数据流的方法和装置公开(公告)号：US20140185593A1
公开(公告)日：2014-07-03
申请号：US14196804
申请日：2014-03-04
发明人： Yan WANG
IPC分类号： H04L5/00
CPC分类号： H04L5/0058 , G06F3/00 , G06F9/46 , G06F13/14 , G06F13/3625 , G06F13/4031 , G06F15/17325
摘要： A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.
摘要翻译： 一种处理系统包括芯片间接口，其包括具有仲裁器的芯片间接口模块，所述仲裁器在每个固定数量的时间片中分配专用时间片，以分配第一优先级以从具有 专用时间片内存储器中的第一个数据路径宽度。 在固定数量的时间片的剩余时间片中，仲裁器进一步在除第一类型之外的一种或多种类型的多个信道之中进行仲裁，其中多个信道对应于与第一数据路径宽度不同的至少一个数据路径宽度，以及 具有更广泛数据通路的通道赢得仲裁。 如果某种类型的信道在时间片中赢得仲裁，仲裁者将进一步仲裁相同类型的两个或多个信道。 还公开了其实现方法。
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10.发明申请公开(公告)号：US20130315258A1
公开(公告)日：2013-11-28
申请号：US13925531
申请日：2013-06-24
发明人： Paolo NARVAEZ , Murat Bog
IPC分类号： H04L12/939
CPC分类号： H04L49/552 , H04J3/062 , H04J3/12 , H04J3/1611 , H04J3/1617 , H04J2203/0069 , H04J2203/0085 , H04J2203/0094 , H04L12/54 , H04L49/351
摘要： A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate desequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to desequencing control commands received from the LCAS control manager.
摘要翻译： 提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，所述系统具有数据对准器，其被配置为根据成员组来对齐输入数据的字节。 该系统还包括LCAS控制管理器，该LCAS控制管理器被配置为响应于从数据对准器输入的数据来生成排序控制命令。 该系统进一步包括解调器，其被配置为根据从LCAS控制管理器接收的预定控制命令来对从数据对准器输入的输入数据进行排序。
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