公开(公告)号：US20060007739A1

公开(公告)日：2006-01-12

申请号：US11130141

申请日：2005-05-17

Applicant: Shinji Takeda ,  Yoshiharu Hirata ,  Naokazu Kuzuno

Inventor： Shinji Takeda ,  Yoshiharu Hirata ,  Naokazu Kuzuno

IPC: G11C11/34

CPC classification number: G11C29/4401 ,  G11C16/04 ,  G11C29/44 ,  G11C29/50004 ,  G11C29/78 ,  G11C2029/0405

Abstract: Data read out from each memory cell in a memory cell array is compared with an expected value by a comparator, and the quality of a memory cell is determined by performing program verify and erase verify. Based on the comparison result of the comparator, a detected defective cell is repaired by replacing it with a spare cell. Every time a defective cell is replaced with a spare cell, information on the defective cell is stored in a register, and whether a defective cell exists and whether the repair is possible are determined on the basis of the information. When the repair is possible, a control circuit is caused to execute control, and a detected defective cell is repaired by replacing it with a spare cell. When the repair is impossible, the defect repair stops.

公开(公告)号：US07123527B2

公开(公告)日：2006-10-17

申请号：US10803936

申请日：2004-03-19

Applicant: Naokazu Kuzuno ,  Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Masaya Kubota

Inventor： Naokazu Kuzuno ,  Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Masaya Kubota

IPC: G11C7/00

CPC classification number: G11C29/24 ,  G11C29/02 ,  G11C29/027 ,  G11C29/78

Abstract: A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.

Abstract translation: 一种冗余熔丝电路，包括用冗余单元替换存储单元阵列中的有缺陷单元的功能，包括熔丝电路，其中有缺陷单元的地址或包括有缺陷单元的块被编程为有缺陷地址， 不存在保险丝的截止，锁存从测试器提供的信号以虚拟方式对缺陷地址进行编程的数据锁存电路，以及基于从冗余单元提供的地址信号替换缺陷单元的比较器 测试器和数据锁存电路的输出信号在冗余熔丝电路的操作确认时间。

公开(公告)号：US07243199B2

公开(公告)日：2007-07-10

申请号：US10609563

申请日：2003-07-01

Applicant: Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno ,  Masaya Kubota

Inventor： Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno ,  Masaya Kubota

IPC: G06F12/14

CPC classification number: G06F21/79 ,  G06F12/1433

Abstract: A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

Abstract translation: 公开了一种存储器数据保护系统，其包括存储器电路，存储安全位和保护位的保护内容指示部分，确定从存储器电路读取数据的许可/禁止和允许/禁止的保护功能电路 根据安全位和保护位将数据写入存储器电路，以及保护功能锁定/解锁电路，其使保护功能电路处于锁定状态，以强制禁止从存储器电路读取数据和写入 在从电源接通开始直到保护功能电路完成从保护内容指示部分读取安全位和保护位到数据总线的时间段内的数据到存储器电路中，并且在经过时间段之后 ，保护功能锁定/解锁电路解锁锁定状态。

公开(公告)号：US07260012B2

公开(公告)日：2007-08-21

申请号：US10777971

申请日：2004-02-13

Applicant: Naokazu Kuzuno ,  Kimio Maruyama ,  Yasuhiro Hegi ,  Kiyoharu Oikawa

Inventor： Naokazu Kuzuno ,  Kimio Maruyama ,  Yasuhiro Hegi ,  Kiyoharu Oikawa

IPC: G11C17/18

CPC classification number: G11C17/18

Abstract: One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.

Abstract translation: 保险丝的一端通过晶体管N1A连接到接地点，另一端连接到节点VaA。 例如，在熔丝连接情况下，当INTV =“H”被输入到晶体管N1A的栅极时，节点VaA变为“L”。 在INTV =“L”时，具有低“导通”电阻的晶体管P1A导通，并且节点VaA被快速预充电。 在INTV =“H”时，晶体管N 1A导通，节点VaA快速放电。

公开(公告)号：US07116592B2

公开(公告)日：2006-10-03

申请号：US11130141

申请日：2005-05-17

Applicant: Shinji Takeda ,  Yoshiharu Hirata ,  Naokazu Kuzuno

Inventor： Shinji Takeda ,  Yoshiharu Hirata ,  Naokazu Kuzuno

IPC: G11C29/00

CPC classification number: G11C29/4401 ,  G11C16/04 ,  G11C29/44 ,  G11C29/50004 ,  G11C29/78 ,  G11C2029/0405

Abstract: Data read out from each memory cell in a memory cell array is compared with an expected value by a comparator, and the quality of a memory cell is determined by performing program verify and erase verify. Based on the comparison result of the comparator, a detected defective cell is repaired by replacing it with a spare cell. Every time a defective cell is replaced with a spare cell, information on the defective cell is stored in a register, and whether a defective cell exists and whether the repair is possible are determined on the basis of the information. When the repair is possible, a control circuit is caused to execute control, and a detected defective cell is repaired by replacing it with a spare cell. When the repair is impossible, the defect repair stops.

Abstract translation: 通过比较器将存储单元阵列中的每个存储单元读出的数据与预期值进行比较，并通过执行程序验证和擦除验证来确定存储单元的质量。 基于比较器的比较结果，通过用备用单元替换检测到的缺陷单元进行修复。 每当有缺陷的单元被替换为备用单元时，有缺陷单元的信息被存储在寄存器中，并且是否存在缺陷单元以及是否可以修复是可能的。 当可以进行修理时，使控制电路执行控制，并通过用备用单元替换来检测检测到的故障单元。 修理不可能时，缺陷修复停止。

公开(公告)号：US06643203B2

公开(公告)日：2003-11-04

申请号：US10230229

申请日：2002-08-29

Applicant: Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno

Inventor： Kiyoharu Oikawa ,  Kimio Maruyama ,  Yasuhiro Watanabe ,  Naokazu Kuzuno

IPC: G11C702

CPC classification number: G11C29/025 ,  G11C7/06 ,  G11C16/28 ,  G11C29/02 ,  G11C2207/005

Abstract: A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.