公开(公告)号：US20070188524A1

公开(公告)日：2007-08-16

申请号：US11704236

申请日：2007-02-09

申请人： Michael Bolotski

发明人： Michael Bolotski

IPC分类号： G09G5/10

CPC分类号： G09G3/2081 ,  G09G3/3208 ,  G09G3/3611 ,  G09G2320/0233 ,  G09G2320/0252

摘要： A method of illuminating a pixel on a display to a desired brightness level that includes dividing a time required to reach a maximum brightness level into one or more time slices, varying a pixel voltage associated with the pixel according to a sequence of voltage values over the one or more time slices, and gradually increasing the brightness of the pixel according to the pixel voltage.

摘要翻译： 一种将显示器上的像素照亮到所需亮度水平的方法，包括将达到最大亮度水平所需的时间分成一个或多个时间片，根据该像素上的电压值序列改变与该像素相关联的像素电压 一个或多个时间片，并且根据像素电压逐渐增加像素的亮度。

公开(公告)号：US6108000A

公开(公告)日：2000-08-22

申请号：US34862

申请日：1998-03-04

申请人： Michael Bolotski ,  Phillip Alvelda

发明人： Michael Bolotski ,  Phillip Alvelda

IPC分类号： G06F1/32 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

CPC分类号： G09G3/2011 ,  G06F1/32 ,  G09G3/3688 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2320/0223 ,  G09G2330/021 ,  G09G2330/023 ,  G09G2330/024

摘要： A system having a display including display circuitry operating at a resonant frequency includes a tunable component, a resonant driver circuit coupled to the tunable component and to the display circuitry, for driving the display circuitry at an output frequency, a power consumption sensor coupled to the resonant driver circuit, for determining the power consumption of the resonant driver circuit, and a control logic coupled to the tunable component and to the power dissipation sensor, for monitoring the power consumption of the resonant driver circuit and for tuning the tunable component in response to the power consumption.

摘要翻译： 具有包括以共振频率工作的显示电路的显示器的系统包括可调组件，耦合到可调组件和显示电路的谐振驱动器电路，用于以输出频率驱动显示电路，耦合到 谐振驱动器电路，用于确定谐振驱动器电路的功耗，以及耦合到可调谐部件和功率耗散传感器的控制逻辑，用于监视谐振驱动器电路的功率消耗并响应于 功耗。

公开(公告)号：US08670004B2

公开(公告)日：2014-03-11

申请号：US12630800

申请日：2009-12-03

申请人： Carlin J. Vieri ,  Michael Bolotski

发明人： Carlin J. Vieri ,  Michael Bolotski

IPC分类号： G09G5/10

CPC分类号： G09G3/3677 ,  G09G2300/0842 ,  G09G2310/0224 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2320/0238

摘要： In an embodiment, a pixel driving circuit comprises: one or more source drivers for enabling a first subpixel of a subpixel pair to receive first data and a second subpixel of the subpixel pair to receive second data; one or more source drivers for driving the first data to the first subpixel and the second data to the second subpixel, wherein the first data is different than the second data.

摘要翻译： 在一个实施例中，像素驱动电路包括：用于使子像素对的第一子像素能够接收第一数据的一个或多个源极驱动器和子像素对的第二子像素以接收第二数据; 一个或多个源驱动器，用于将第一数据驱动到第一子像素，第二数据驱动到第二子像素，其中第一数据不同于第二数据。

公开(公告)号：US20100231614A1

公开(公告)日：2010-09-16

申请号：US12630800

申请日：2009-12-03

申请人： Carlin J. Vieri ,  Michael Bolotski

发明人： Carlin J. Vieri ,  Michael Bolotski

IPC分类号： G09G5/10

CPC分类号： G09G3/3677 ,  G09G2300/0842 ,  G09G2310/0224 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2320/0238

摘要： In an embodiment, a pixel driving circuit comprises: one or more source drivers for enabling a first subpixel of a subpixel pair to receive first data and a second subpixel of the subpixel pair to receive second data; one or more source drivers for driving the first data to the first subpixel and the second data to the second subpixel, wherein the first data is different than the second data.

摘要翻译： 在一个实施例中，像素驱动电路包括：用于使子像素对的第一子像素能够接收第一数据的一个或多个源极驱动器和子像素对的第二子像素以接收第二数据; 一个或多个源驱动器，用于将第一数据驱动到第一子像素，第二数据驱动到第二子像素，其中第一数据不同于第二数据。

公开(公告)号：US06567061B1

公开(公告)日：2003-05-20

申请号：US09548052

申请日：2000-04-12

申请人： Michael Bolotski ,  Phillip Alvelda

发明人： Michael Bolotski ,  Phillip Alvelda

IPC分类号： G09G336

CPC分类号： G09G3/006 ,  G09G3/3611 ,  G09G2320/0233 ,  G09G2320/0285

摘要： A method for operating a display having substrates and a plurality of capacitors formed at predetermined locations between the substrates includes measuring a capacitance for each of the plurality of capacitors, determining a cell gap for each of the plurality of capacitors in response to the capacitance for each of the plurality of capacitors, determining a cell gap relationship between the substrates in response to the cell gap for each of the plurality of capacitors and in response to the predetermined locations on the display, and determining a first intensity compensating value for a first pixel on an active region of the display in response to the cell gap relationship between the substrates and in response to a location of the first pixel on the display.

摘要翻译： 一种用于操作具有基板的显示器和形成在基板之间的预定位置处的多个电容器的方法包括测量多个电容器中的每一个的电容，响应于每个电容器的电容确定多个电容器中的每一个的单元间隙 响应于所述多个电容器中的每一个的单元间隙以及响应于所述显示器上的预定位置来确定所述基板之间的单元间隙关系，以及确定所述多个电容器中的第一像素的第一强度补偿值 响应于基板之间的单元间隙关系和响应于显示器上的第一像素的位置的显示器的有效区域。

公开(公告)号：US07292214B2

公开(公告)日：2007-11-06

申请号：US09480986

申请日：2000-01-10

申请人： Michael Bolotski ,  David Huffman

发明人： Michael Bolotski ,  David Huffman

IPC分类号： G09G3/36 ,  G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3648 ,  G09G3/34 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0235 ,  G09G2310/0251 ,  G09G2310/063 ,  G09G2320/0252 ,  G09G2330/12

摘要： A method for operating a display having a plurality of pixel elements includes applying a transition voltage to the plurality of pixel elements, applying a first paint voltage to one pixel element of the plurality pixel elements, waiting a predetermined time period, illuminating the one pixel element, applying the transition voltage to the plurality of pixel elements, applying a second paint voltage to the one pixel element elements, waiting the predetermined time period, and illuminating the one pixel element. The transition voltage is different from the first paint voltage applied to the one pixel element.

摘要翻译： 一种用于操作具有多个像素元件的显示器的方法包括向多个像素元件施加转变电压，向多个像素元件中的一个像素元件施加第一涂料电压，等待预定时间周期，照亮所述一个像素元件 对所述多个像素元件施加所述转移电压，对所述一个像素元件施加第二涂料电压，等待所述预定时间周期，以及照射所述一个像素元件。 转换电压与施加到一个像素元件的第一涂漆电压不同。

公开(公告)号：US6052773A

公开(公告)日：2000-04-18

申请号：US471836

申请日：1995-06-06

申请人： Andre DeHon ,  Michael Bolotski ,  Thomas F. Knight, Jr.

发明人： Andre DeHon ,  Michael Bolotski ,  Thomas F. Knight, Jr.

IPC分类号： G06F15/78 ,  G06F15/00

CPC分类号： G06F9/30181 ,  G06F15/7867 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3897

摘要： A single chip microprocessor or memory device has reprogrammable characteristics according to the invention. In the case of the microprocessor, a fixed processing cell is provided as is common to perform logic calculations. A portion of the chip silicon real-estate, however, is dedicated a programmable gate array. This feature enables application-specific configurations to allow adaptation to the particular time-changing demands of the microprocessor and provide the functionality required to best serve those demands. This yields application acceleration and in system-specific functions. In other cases the configurable logic acts as network interface, which allows the same basic processor design to function in any environment to which the interface can adapt.The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units. These features lessen the impact of the data bottle-neck associated with bus communications, since the processing capability is moved to the memory in the form programmable logic, which can be configured to the needs of the specific application. The inherently large on-chip bandwidth can then be utilized to increase the speed at which bulk data is processed.

摘要翻译： 单芯片微处理器或存储器件具有根据本发明的可编程特性。 在微处理器的情况下，提供固定的处理单元，以便执行逻辑计算。 然而，芯片硅的部分区域专用于可编程门阵列。 此功能使特定应用的配置能够适应微处理器的特定时变需求，并提供最佳服务于这些需求所需的功能。 这产生了应用程序加速和系统特定的功能。 在其他情况下，可配置逻辑充当网络接口，这允许相同的基本处理器设计在接口可以适应的任何环境中起作用。 本发明还涉及具有多个存储体和与存储体相关联的可配置逻辑单元的存储器件。 提供互连以实现可配置逻辑单元之间的通信。 这些功能可以减轻与总线通信相关的数据瓶颈的影响，因为处理能力可以以可编程逻辑的形式移动到存储器，可以根据具体应用的需要进行配置。 然后可以利用固有的大的片上带宽来提高处理批量数据的速度。

公开(公告)号：US07876299B2

公开(公告)日：2011-01-25

申请号：US11704236

申请日：2007-02-09

申请人： Michael Bolotski

发明人： Michael Bolotski

IPC分类号： G09G3/36

CPC分类号： G09G3/2081 ,  G09G3/3208 ,  G09G3/3611 ,  G09G2320/0233 ,  G09G2320/0252

摘要： A method of illuminating a pixel on a display to a desired brightness level that includes dividing a time required to reach a maximum brightness level into one or more time slices, varying a pixel voltage associated with the pixel according to a sequence of voltage values over the one or more time slices, and gradually increasing the brightness of the pixel according to the pixel voltage.

摘要翻译： 一种将显示器上的像素照亮到所需亮度水平的方法，包括将达到最大亮度水平所需的时间分成一个或多个时间片，根据该像素上的电压值序列改变与该像素相关联的像素电压 一个或多个时间片，并且根据像素电压逐渐增加像素的亮度。

公开(公告)号：US5742180A

公开(公告)日：1998-04-21

申请号：US386851

申请日：1995-02-10

申请人： Andre DeHon ,  Thomas F. Knight, Jr. ,  Edward Tau ,  Michael Bolotski ,  Ian Eslick ,  Derrick Chen ,  Jeremy Brown

发明人： Andre DeHon ,  Thomas F. Knight, Jr. ,  Edward Tau ,  Michael Bolotski ,  Ian Eslick ,  Derrick Chen ,  Jeremy Brown

IPC分类号： G06F15/78 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F15/7867 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/1776

摘要： An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural other gates. Consequently, a broad range of logic combinations are possible. The gates further include locally stored multiple contexts dictating different combinatorial logic operations performed by the gates. The contexts increase the logic operations performable by the gate and the fact that the contexts are locally stored enables better integration and speed. Only a context instruction needs to be distributed among programmable gates. A context signal generator is included that generates a context signal indicating a change in an active one of the contexts. This active context dictates the logic operations of the gates that commonly receive by the signal. Since the contexts information is stored on the gate array, and specifically locally, the context signal can change as fast as every clock cycle of the programmable gate array. To increase functionality, context memory arrays, which store context programming information, are separately addressable so that a new truth table is storable in a first one of the context memory arrays while a truth table of a second one of the context memory arrays is dictating the logic operations performed by the gates. As a result, the functionality of each programmable gate can be increased by increasing the number of available functions for that programmable gate.

摘要翻译： 集成的动态可编程门阵列包括可编程门的二维阵列。 这些门可以被实现为查找表，但是具有可编程互连的硬连线也是可能的。 每个门从多个其他门接收多个输入逻辑信号。 因此，广泛的逻辑组合是可能的。 门还包括本地存储的多个上下文，其规定由门执行的不同的组合逻辑操作。 上下文增加了由门执行的逻辑操作以及上下文本地存储的事实，可以实现更好的集成和速度。 只有上下文指令需要在可编程门之间分配。 包括上下文信号发生器，其产生指示上下文中活动的一个的改变的上下文信号。 该有源上下文指示通常由信号接收的门的逻辑运算。 由于上下文信息存储在门阵列上，特别是在本地，上下文信号可以像可编程门阵列的每个时钟周期一样快地改变。 为了增加功能，存储上下文编程信息的上下文存储器阵列是可单独寻址的，使得新的真值表可存储在上下文存储器阵列中的第一个存储器阵列中，而第二个上下文存储器阵列的真值表指示 由门执行的逻辑操作。 结果，可以通过增加可编程门的可用功能的数量来增加每个可编程门的功能。