公开(公告)号：US20110125946A1

公开(公告)日：2011-05-26

申请号：US12916668

申请日：2010-11-01

Applicant: Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

Inventor： Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

IPC: G06F13/18 ,  G06F12/06

CPC classification number: G06F13/161 ,  G06F13/1673 ,  Y02D10/14

Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract translation: 存储器访问仲裁允许共享存储器既用作处理器的存储器又用作数据流的缓冲器，包括仲裁器单元，其顺序地对存储器的访问请求进行分配，并在一个循环周期中传送数据块 根据数据传输所需的带宽，设置传输块的优先级，使得通过传输块的交替传送来满足数据传输所需的带宽，并且执行对处理器的访问，其具有为 在一个循环周期中从处理器到存储器的访问时间，使得来自具有最高优先级并且具有预定传送长度的处理器的访问对传输块之间的预定间隔中的数据流传输的带宽的影响较小。

公开(公告)号：US06357030B1

公开(公告)日：2002-03-12

申请号：US09216014

申请日：1998-12-16

Applicant: Masayuki Demura ,  Tetsuya Tamura ,  Akira Sasaki ,  Hiroshi Itagaki

Inventor： Masayuki Demura ,  Tetsuya Tamura ,  Akira Sasaki ,  Hiroshi Itagaki

IPC: H03M1315

CPC classification number: H03M13/1515 ,  G11B20/1813 ,  H03M13/29 ,  H03M13/2903 ,  H03M13/2909

Abstract: A method and apparatus for efficiently encoding an ECC block for improving writing performance of a storage device using an ECC block format having a linear code such as a Reed-Solomon code is described. When the data f1 of a part of data sectors among a plurality of data sectors which form an ECC block F1 having a PO portion q1 formed with a linear code such as a Reed-Solomon code is updated with data f2 to obtain the ECC block F2 having the updated PO portion q2, the ECC block F1+F2 of the exclusive OR of the source data part of the ECC block F1 before updating and the ECC block F2 after updating is taken, so that the XOR of f1 and f2 (i.e. f1+f2) of the data f1 to be updated and the updated data f2 is obtained. The XOR of non-updated data sectors is 0. Then, when the ECC block F1+F2 of the XOR is encoded, the PO portion in the form of the XOR q1+q2 is obtained in accordance with the linearity of the Reed-Solomon code. Thus, q2 can be gained based on the exclusive OR of q1+q2 and q1, resulting in the ability to write out the data more efficiently.

Abstract translation: 描述了一种使用具有诸如里德 - 索罗门码等线性码的ECC块格式来有效地编码用于提高存储装置的写入性能的ECC块的方法和装置。 当用数据f2更新形成具有诸如Reed-Solomon码的线性码形成的PO部分q1的ECC块F1的多个数据扇区中的数据扇区的数据f1，以获得ECC块F2 具有更新的PO部分q2时，获取更新前的ECC块F1的源数据部分与更新后的ECC块F2的异或的ECC块F1 + F2，使得f1和f2的XOR（即f1 + f2），并且获得更新数据f2。 未更新的数据扇区的异或为0.然后，当XOR的ECC块F1 + F2被编码时，根据Reed-Solomon的线性度，获得XOR q1 + q2形式的PO部分 码。 因此，可以基于q1 + q2和q1的异或获得q2，从而能够更有效地写入数据。

公开(公告)号：US20100177421A1

公开(公告)日：2010-07-15

申请号：US12351725

申请日：2009-01-09

Applicant: Masayuki Demura ,  Glen Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

Inventor： Masayuki Demura ,  Glen Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

IPC: G11B5/09 ,  G11B15/00

CPC classification number: G11B20/1201 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1222 ,  G11B2220/90 ,  H03M13/271 ,  H03M13/2909

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract translation: 方法，逻辑，设备和计算机程序产品写入数据，包括少于一个完整的数据集，到磁带。 从主机接收数据，发出不交错命令，并计算C1和C2 ECC。 然后形成Codeword Quad（CQ）集合。 将数据集的至少一个CQ集以非交错方式写入磁带，并且数据集信息表（DSIT）被写入紧跟在至少一个写入的CQ集之后的磁带上。 可以使用地址变换来取消交织。 编写CQ集可以包括将CQ集的多个连续实例写入磁带以保持ECC能力的有效性。

公开(公告)号：US06421807B1

公开(公告)日：2002-07-16

申请号：US09343946

申请日：1999-06-30

Applicant: Akio Nakamura ,  Tetsuya Tamura ,  Masayuki Demura ,  Hironobu Nagura

Inventor： Akio Nakamura ,  Tetsuya Tamura ,  Masayuki Demura ,  Hironobu Nagura

IPC: H03M1300

CPC classification number: H03M13/1535 ,  H03M13/158

Abstract: An apparatus and method for decoding data encoded in a linear cyclic code with less hardware than the prior art decoding apparatus without sacrificing the processing speed are described. The polynomial arithmetic part 14 derives polynomials &sgr;(x), &ohgr;(x) by repeating calculation of the following Qi(x), exchange of polynomials between the register U_reg 180 and the register X_reg 184, and exchange of polynomials between the register Y_reg 182 and the register Z_reg 186 until the degree (deg Xreg) of the polynomial in the register X_reg 184 becomes smaller than [(d−h+1)/2] to solve the following recursive formula. [recursive formula]=&sgr;i(x)=&sgr;i−2(x)+Qi(x)·&sgr;i−1(x) &ohgr;i(x)=&ohgr;i−2(x)+Qi(x)·&ohgr;i−1(x) where Qi(x) is a quotient of &ohgr;i−2(x)/&ohgr;i−1(x) &sgr;−1(x)=1, &ohgr;−1(x)=x2t &sgr;0(x)=1, &ohgr;0(x)=M(x)

Abstract translation: 描述了以比现有技术的解码装置更少的硬件对以循环码进行编码的数据进行解码而不牺牲处理速度的装置和方法。 多项式运算部分14通过重复计算以下的Qi（x），在寄存器U_reg 180和寄存器X_reg 184之间的多项式的交换以及寄存器Y_reg 182之间的多项式的交换来导出多项式sigma（x），ω（x） 和寄存器Z_reg 186，直到寄存器X_reg 184中的多项式的度（deg Xreg）变得小于[（d-h + 1）/ 2]来求解以下递归公式。其中，Qi（x）是 omega-2（x）/ omegai-1（x）sigma-1（x）= 1，ω-1（x）= x2t sigma0（x）= 1，omega0（x）= M

公开(公告)号：US08412891B2

公开(公告)日：2013-04-02

申请号：US12916668

申请日：2010-11-01

Applicant: Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

Inventor： Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

IPC: G06F12/12 ,  G06F13/18 ,  G06F13/34

CPC classification number: G06F13/161 ,  G06F13/1673 ,  Y02D10/14

Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract translation: 存储器访问仲裁允许共享存储器既用作处理器的存储器又用作数据流的缓冲器，包括仲裁器单元，其顺序地对存储器的访问请求进行分配，并在一个循环周期中传送数据块 根据数据传输所需的带宽，设置传输块的优先级，使得通过传输块的交替传送来满足数据传输所需的带宽，并且执行对处理器的访问，其具有为 在一个循环周期中从处理器到存储器的访问时间，使得来自具有最高优先级并且具有预定传送长度的处理器的访问对传输块之间的预定间隔中的数据流传输的带宽的影响较小。

公开(公告)号：US07965462B2

公开(公告)日：2011-06-21

申请号：US12351725

申请日：2009-01-09

Applicant: Masayuki Demura ,  Glen A. Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

Inventor： Masayuki Demura ,  Glen A. Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

IPC: G11B20/16

CPC classification number: G11B20/1201 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1222 ,  G11B2220/90 ,  H03M13/271 ,  H03M13/2909

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract translation: 方法，逻辑，设备和计算机程序产品写入数据，包括少于一个完整的数据集，到磁带。 从主机接收数据，发出不交错命令，并计算C1和C2 ECC。 然后形成Codeword Quad（CQ）集合。 将数据集的至少一个CQ集以非交错方式写入磁带，并且数据集信息表（DSIT）被写入紧跟在至少一个写入的CQ集之后的磁带上。 可以使用地址变换来取消交织。 编写CQ集可以包括将CQ集的多个连续实例写入磁带以保持ECC能力的有效性。

公开(公告)号：US6079046A

公开(公告)日：2000-06-20

申请号：US057998

申请日：1998-04-09

Applicant: Tetsuya Tamura ,  Masayuki Demura ,  Hiroshi Itagaki ,  Kohji Yamada

Inventor： Tetsuya Tamura ,  Masayuki Demura ,  Hiroshi Itagaki ,  Kohji Yamada

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03M13/00 ,  H04L13/08

CPC classification number: G11B20/1813 ,  G11B20/10527

Abstract: It is one object of the present invention to perform efficient data transfer processing wherein, during decoding using a combination of product coding and erasure correction, real-time correction can be performed. To achieve the above object, provided is a method whereby a transfer mode is dynamically altered, in accordance with the state of a decoder, and in additional buffer, consisting of two banks, is added, so that the speed for the data transferring relative to the decoder is increased.

Abstract translation: 本发明的一个目的是执行有效的数据传输处理，其中在使用产品编码和擦除校正的组合的解码期间，可以执行实时校正。 为了实现上述目的，提供了一种根据解码器的状态动态地改变传输模式的方法，并且添加由两个组组成的附加缓冲器，使得数据传输的速度相对于 解码器增加。

公开(公告)号：US06553533B2

公开(公告)日：2003-04-22

申请号：US09245803

申请日：1999-02-05

Applicant: Masayuki Demura ,  Hironobu Nagura ,  Tetsuya Tamura ,  Keisuke Tanaka

Inventor： Masayuki Demura ,  Hironobu Nagura ,  Tetsuya Tamura ,  Keisuke Tanaka

IPC: G11C2900

CPC classification number: G06F11/1008 ,  G11B20/10 ,  G11B20/18 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/293

Abstract: A method and apparatus for detecting and correcting errors and erasures in product-coded data arrays by iterative syndrome processing array data in row major order and column major order. A first dense map is formed for classifying each row containing location indicia of random errors, their correction patterns, and pointers to rows containing erasure errors. This map is used to effectuate row array random error corrections in place in memory. A second dense map is formed of location indicia and correction patterns for each pair adjacent position within a column containing erasure errors as indexed by a counterpart row pointer. The second map is used to effectuate column array erasure corrections and random error corrections in place in memory.

Abstract translation: 一种检测和校正产品编码数据阵列中的错误和消除误差的方法和装置，通过迭代校正处理阵列数据以行主序和列主序列。 形成第一密集地图，用于将包含随机错误的位置标记，它们的校正模式和指向包含擦除错误的行的指针的每行分类。 该映射用于在存储器中实现行阵列随机误差校正。 第二密集地图由位置标记和校正图案形成，每个对相邻位置在包含由对应行指针索引的擦除错误的列内。 第二个映射用于在存储器中实现列阵列擦除校正和随机错误校正。