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    Encrypting apparatus
    1.
    发明申请
    Encrypting apparatus 审中-公开
    加密设备

    公开(公告)号：US20110176673A1

    公开(公告)日：2011-07-21

    申请号：US13064460

    申请日：2011-03-25

    申请人： Dai Yamamoto ,  Kouichi Itoh ,  Masayoshi Isobe ,  Souichi Okada

    发明人： Dai Yamamoto ,  Kouichi Itoh ,  Masayoshi Isobe ,  Souichi Okada

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0643 ,  G09C1/00 ,  H04L2209/122

    摘要： An encrypting apparatus includes a digest part using a SHA-2 algorithm of which a basic unit of operation is 32*Y (Y=1 or 2) bits. The digest part includes a shift register including a series of registers, and a predetermined number of adders performing an addition operation based on data stored in the shift register. The shift register includes a (32*Y)/X-bit register, where X=2k (k is an integer such that 1≦k≦4 when Y=1 and 1≦k≦5 when Y=2). Each of the adders has a data width of (32*Y)/X bits and performs the addition operation in each cycle in which the data stored in the shift register is shifted between the registers with the data width of (32*Y)/X bits.

    摘要翻译： 加密装置包括使用SHA-2算法的摘要部分，其基本操作单元是32×Y（Y = 1或2）位。 摘要部分包括一个包括一系列寄存器的移位寄存器和一个预定数量的加法器，它们基于存储在移位寄存器中的数据执行加法运算。 移位寄存器包括一个（32 * Y）/ X位寄存器，其中X = 2k（k是当Y = 1和1＆nlE; k＆nlE; 5，当Y = 2时，1＆nlE; k＆nlE; 4的整数）。 每个加法器的数据宽度为（32×Y）/ X位，并且在存储在移位寄存器中的数据在数据宽度为（32 * Y）/ X位的寄存器之间移位的每个周期中执行相加操作， X位。

    CMOS inverter
    2.
    发明授权
    CMOS inverter 有权
    CMOS逆变器

    公开(公告)号：US06794905B2

    公开(公告)日：2004-09-21

    申请号：US10094824

    申请日：2002-03-11

    申请人： Masatoshi Sato ,  Masayoshi Isobe

    发明人： Masatoshi Sato ,  Masayoshi Isobe

    IPC分类号： H03K19084

    CPC分类号： H03K19/01707

    摘要： A CMOS inverter capable of operating at low voltages is provided. The gate of a p-channel MOS transistor and the gate of an n-channel MOS transistor are AC coupled to an input terminal via first and second capacitors, respectively. Signals whose amplitude centers are optimized according to the threshold voltages of the p- and n-channel MOS transistors by bias voltages from first and second variable voltage sources, respectively, are supplied to the gates of these MOS transistors. In consequence, the CMOS inverter can operate at high speeds at low power supply voltages without being affected by the threshold voltages.

    摘要翻译： 提供能够在低电压下工作的CMOS逆变器。 p沟道MOS晶体管的栅极和n沟道MOS晶体管的栅极分别经由第一和第二电容器耦合到输入端子。 根据来自第一和第二可变电压源的偏置电压，根据p沟道MOS晶体管和n沟道MOS晶体管的阈值电压优化其振幅中心的信号被提供给这些MOS晶体管的栅极。 因此，CMOS反相器可以在低电源电压下以高速运行，而不受阈值电压的影响。

    SWAP CIRCUIT FOR COMMON KEY BLOCK CIPHER AND ENCRYPTION/DECRYPTION CIRCUIT INCLUDING THE SAME
    5.
    发明申请
    SWAP CIRCUIT FOR COMMON KEY BLOCK CIPHER AND ENCRYPTION/DECRYPTION CIRCUIT INCLUDING THE SAME 审中-公开
    用于常用键盘盖的切换电路和包括其的加密/分解电路

    公开(公告)号：US20100111295A1

    公开(公告)日：2010-05-06

    申请号：US12580462

    申请日：2009-10-16

    申请人： Souichi OKADA ,  Masayoshi Isobe

    发明人： Souichi OKADA ,  Masayoshi Isobe

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0637 ,  H04L2209/12

    摘要： An encryption/decryption circuit includes a swap circuit for outputting each of text data and initialization vector data which are input from an input terminal to either a first or second output terminal in accordance with one of modes of operation, an encryption/decryption processing unit to which one of the text data and the initialization vector data are input from the first output terminal and which performs encryption processing and decryption processing on the data, and an exclusive OR processing unit to which another one of the initialization vector data and the text data are input from the second output terminal and which performs an exclusive OR operation on the data.

    摘要翻译： 加密/解密电路包括交换电路，用于根据操作模式之一输出从输入端输入到第一或第二输出端的文本数据和初始化矢量数据;加密/解密处理单元， 文本数据和初始化矢量数据中的哪一个从第一输出端输入，并且对该数据进行加密处理和解密处理;以及异或处理单元，其中另一个初始化向量数据和文本数据是 从第二输出端子输入并对数据执行异或运算。