公开(公告)号：US07515369B2

公开(公告)日：2009-04-07

申请号：US11388377

申请日：2006-03-24

申请人： Takao Sugawara ,  Motomu Takatsu ,  Masaru Sawada

发明人： Takao Sugawara ,  Motomu Takatsu ,  Masaru Sawada

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B5/09 ,  G11B20/18

摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

摘要翻译： 定时恢复单元从再现数据的头部区域检测相位偏移和频率偏移，并且最初校正它们。 定时恢复单元将已经通过固定时钟将头重放信号离散的数据存储到缓冲器中。 相位偏移检测器与将数据写入缓冲器的操作并行地检测与数据头区域的相位偏移。 同时，频率偏移检测器与将数据写入缓冲器的操作并行地检测数据头区域的频率偏移。 检测到的相位偏移的校正值和检测到的频率偏移的校正值最初被设置为数字PLL。 当从缓冲器中读出数据时，在头部区域中执行频率导入和相位导入。

公开(公告)号：US20080297240A1

公开(公告)日：2008-12-04

申请号：US12125609

申请日：2008-05-22

申请人： Hideaki Kondo ,  Masaru Sawada ,  Norio Murakami ,  Syoichi Masui

发明人： Hideaki Kondo ,  Masaru Sawada ,  Norio Murakami ,  Syoichi Masui

IPC分类号： H04B1/10 ,  H03B1/04

CPC分类号： H03H11/1291 ,  H03H7/12 ,  H03H2007/0192 ,  H03H2011/0494

摘要： A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.

摘要翻译： 滤波器电路包括低通滤波器和校准低通滤波器的频率特性的校准电路。 校准电路包括负反馈电路和控制电路。

公开(公告)号：US07248188B2

公开(公告)日：2007-07-24

申请号：US11377124

申请日：2006-03-16

申请人： Toshio Ito ,  Masaru Sawada ,  Toshihiko Morita

发明人： Toshio Ito ,  Masaru Sawada ,  Toshihiko Morita

IPC分类号： H03M7/00

CPC分类号： H03M5/145 ,  G11B20/1866

摘要： An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.

摘要翻译： 编码比特串生成单元生成通过对输入比特串进行扰频编码的比特串。 直流分量评估单元在逐位移位时，选择由编码比特串生成单元生成的比特串中具有预定宽度的比特串，并且评估所选择的比特串中的直流分量 。 基于直流分量评估单元的评价结果​​，位串提取单元提取具有抑制的直流分量的比特串。

公开(公告)号：US06798832B1

公开(公告)日：2004-09-28

申请号：US09536184

申请日：2000-03-27

申请人： Yoshitaka Nakata ,  Masaru Sawada ,  Tsunehiko Moriuchi

发明人： Yoshitaka Nakata ,  Masaru Sawada ,  Tsunehiko Moriuchi

IPC分类号： H04H740

CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B20/10055

摘要： A semiconductor circuit includes a decision feedback equalizer (DFE) for waveform-equalizing an input signal and generating a waveform-equalized input signal. The DFE compares the waveform-equalized signal with a predetermined reference voltage to generate a decision signal having first and second decision values and an error signal which lies between the waveform-equalized signal and the decision signal. A dispersion value calculator is connected to the DFE, calculates first and second dispersion values of the first and second decision values of the decision signal using the error signal, and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected to the DFE and the dispersion value calculator. The asymmetry compensator receives the input signal and corrects an asymmetry in the input signal in accordance with the compensation signal and supplies the corrected input signal to the DFE. The semiconductor device may be used in a hard disk control circuit.

摘要翻译： 半导体电路包括用于对输入信号进行波形均衡并产生波形均衡的输入信号的判决反馈均衡器（DFE）。 DFE将波形均衡信号与预定参考电压进行比较，以产生具有第一和第二判定值的判定信号和位于波形均衡信号和判决信号之间的误差信号。 色散值计算器连接到DFE，使用误差信号计算判定信号的第一和第二判定值的第一和第二色散值，并使用第一和第二色散值产生补偿信号。 不对称补偿器连接到DFE和色散值计算器。 不对称补偿器根据补偿信号接收输入信号并校正输入信号的不对称性，并将校正的输入信号提供给DFE。 半导体器件可以用在硬盘控制电路中。

公开(公告)号：US06671115B2

公开(公告)日：2003-12-30

申请号：US09526277

申请日：2000-03-15

申请人： Hiroko Haraguchi ,  Masaru Sawada

发明人： Hiroko Haraguchi ,  Masaru Sawada

IPC分类号： G11B509

CPC分类号： G11B21/10 ,  G11B5/5526 ,  G11B5/59605 ,  G11B5/59644 ,  G11B5/59655 ,  G11B19/247 ,  G11B21/083

摘要： A servo signal processing apparatus for processing a servo signal corresponding to servo information from a servo area on a recording medium for controlling a head. The servo area includes a servo mark area for storing a servo mark indicative of a head of the servo area, a gray mark area for storing a gray mark indicative of a head of information for position control for the head, and a gray code area for storing information. An A-D converter converts the servo signal to digital data. A digital filter filters the converted data based on a sampling clock, and outputs the filtered digital data. A servo mark detector detects a servo mark based on a continuity of a first predetermined logical value. A gray code decoder detects a gray code based on a continuity of a predetermined logical value. The gray code decoder decodes information stored in a gray code area following the detected gray mark.

公开(公告)号：US6061311A

公开(公告)日：2000-05-09

申请号：US991878

申请日：1997-12-16

申请人： Shigetaka Asano ,  Masaru Sawada

发明人： Shigetaka Asano ,  Masaru Sawada

IPC分类号： G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  G11B5/09

CPC分类号： G11B20/1833 ,  G11B20/1217 ,  G11B27/3027 ,  G11B2220/2562

摘要： A device for reproducing data recorded on a recording medium, such as a magnetic disk or an optical disk, includes a data reading apparatus and a data reproducing apparatus. The data reading apparatus reads sector data from the reading medium, including data, synch-byte signals and control signals, and generates a clock signal. The data reading apparatus reproduces the recorded data in accordance with the clock signal. When a synch-byte signal is detected by the reading apparatus, transmission of control signals to the reproducing apparatus is inhibited. In addition, lost data is recovered using other data and an ECC code.

摘要翻译： 用于再现记录在诸如磁盘或光盘的记录介质上的数据的装置包括数据读取装置和数据再现装置。 数据读取装置从读取介质读取包括数据，同步字节信号和控制信号的扇区数据，并产生时钟信号。 数据读取装置根据时钟信号再现记录的数据。 当读取装置检测到同步字节信号时，禁止向再现装置发送控制信号。 此外，使用其他数据和ECC代码恢复丢失的数据。

公开(公告)号：US5870591A

公开(公告)日：1999-02-09

申请号：US691411

申请日：1996-08-02

申请人： Masaru Sawada

发明人： Masaru Sawada

IPC分类号： G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  H03L7/091 ,  H03L7/099 ,  G06F1/04

CPC分类号： H03L7/0993 ,  G11B5/012 ,  G11B5/553 ,  G11B5/59622 ,  H03L7/091

摘要： A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.

摘要翻译： 数字运算电路包括多个算术运算块，控制信号发生器和选择器。 多个算术运算块并行地接收多个数字输入信号，并对接收的数字输入信号进行不同的算术运算，以输出运算结果信号。 控制信号发生器接收多个数字输入信号，并根据数字输入信号产生控制信号。 选择器响应于控制信号选择一个操作结果信号，以输出所选择的运算结果信号。 在控制信号发生器将控制信号提供给选择器之后，一旦选择的操作结果信号被提供给选择器，选择器输出所选择的运算结果信号。

公开(公告)号：US20120218049A1

公开(公告)日：2012-08-30

申请号：US13310069

申请日：2011-12-02

申请人： Masaru SAWADA

发明人： Masaru SAWADA

IPC分类号： H03L7/097

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0812

摘要： A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.

摘要翻译： PLL包括：电荷泵均衡器，其具有多个电荷泵，根据相差信号产生充电电流，每个相位差信号通过将相位差信号延迟不同时间而产生，并将由该电荷产生的充电电流相加并输出 泵; 具有环路滤波器和压控振荡器的理想特性的复制电路，其输入具有相差信号的相位差的数字值，并根据理想特性生成复制输出; 以及系数发生电路，对所述差分信号和所述相位差信号的相关值进行平滑，以产生电荷泵系数，并将其反馈到所述多个电荷泵。 电荷泵产生各自具有对应于电荷泵系数的电流值的充电电流。

公开(公告)号：US20100120375A1

公开(公告)日：2010-05-13

申请号：US12692325

申请日：2010-01-22

申请人： Masaru SAWADA ,  Hideaki KONDO ,  Norio MURAKAMI

发明人： Masaru SAWADA ,  Hideaki KONDO ,  Norio MURAKAMI

IPC分类号： H04B1/40

CPC分类号： H04B1/48 ,  H04B1/0458

摘要： A transmitting and receiving circuit includes a transmitting side amplifier circuit amplifying a transmission signal transmitted from an antenna, a receiving side amplifier circuit amplifying a reception signal received by the antenna and being electrically connected to the a transmitting side amplifier circuit, a first matching circuit matching the antenna and the transmitting side amplifier circuit, a second matching circuit matching the antenna and the receiving side amplifier circuit, a first current source circuit capable of controlling an operating state and setting a first connection point between the first matching circuit and an output terminal of the transmitting side amplifier circuit to a given voltage, and a second current source circuit capable of controlling an operating state and setting a second connection point between the second matching circuit and an input terminal of the receiving side amplifier circuit to a given voltage.

摘要翻译： 发送和接收电路包括放大从天线发送的发送信号的发送侧放大器电路，放大由天线接收的并与发送侧放大器电路电连接的接收信号的接收侧放大器电路，第一匹配电路匹配 天线和发送侧放大器电路，匹配天线和接收侧放大器电路的第二匹配电路，能够控制操作状态并将第一匹配电路和输出端之间的第一连接点设置为第一电流源电路的第一电流源电路 所述发送侧放大器电路为给定电压;以及第二电流源电路，其能够控制操作状态，并将所述第二匹配电路和所述接收侧放大器电路的输入端之间的第二连接点设定为给定电压。

公开(公告)号：US20060220926A1

公开(公告)日：2006-10-05

申请号：US11201895

申请日：2005-08-11

申请人： Toshio Ito ,  Masaru Sawada ,  Toshihiko Morita

发明人： Toshio Ito ,  Masaru Sawada ,  Toshihiko Morita

IPC分类号： H03M7/00

CPC分类号： G11B20/10009 ,  G11B20/10194 ,  G11B20/1426 ,  G11B2020/1457

摘要： An encoder includes an encoded-bit-string generating unit that generates a plurality of bit strings encoded by scrambling with respect to an input bit string; a DC-component evaluating unit that selects a bit string having a predetermined width in the bit strings generated by the encoded-bit-string generating unit, while shifting bits one by one or every m-bits, where m is a positive integer, and evaluates the DC component in each of the bit strings selected; and a bit-string extracting unit that extracts a bit string with suppressed DC component from among the bit strings encoded, based on a result of an evaluation by the direct-current-component evaluating unit.

摘要翻译： 编码器包括编码比特串生成单元，其生成通过相对于输入比特串的加扰编码的多个比特串; DC分量评估单元，在由位编码比特串生成单元生成的比特串中选择具有预定宽度的比特串，同时移位比特一个或每个m比特，其中m是正整数，以及 评估所选择的每个位串中的直流分量; 以及位串提取单元，其基于直流分量评估单元的评估结果，从编码的比特串中提取具有抑制的DC分量的比特串。