发明申请
- 专利标题: PLL
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申请号: US13310069申请日: 2011-12-02
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公开(公告)号: US20120218049A1公开(公告)日: 2012-08-30
- 发明人: Masaru SAWADA
- 申请人: Masaru SAWADA
- 申请人地址: JP Yokohama-shi
- 专利权人: FUJITSU SEMICONDUCTOR LIMITED
- 当前专利权人: FUJITSU SEMICONDUCTOR LIMITED
- 当前专利权人地址: JP Yokohama-shi
- 优先权: JP2011-037832 20110224
- 主分类号: H03L7/097
- IPC分类号: H03L7/097
摘要:
A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.
公开/授权文献
- US08339206B2 PLL 公开/授权日:2012-12-25
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