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    Hardware component graph to hardware description language translation method
    1.
    发明授权
    Hardware component graph to hardware description language translation method 失效
    硬件组件图到硬件描述语言翻译方法

    公开(公告)号：US07430727B2

    公开(公告)日：2008-09-30

    申请号：US11440065

    申请日：2006-05-25

    申请人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

    发明人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.

    摘要翻译： 一种HCG到HDL的翻译方法，可以自动生成VHDL代码。 该方法读取硬件组件图（HCG）以找到起始节点并获取起始节点的相应硬件组件子图，分析起始节点的所有信息，从而添加输入和输出组件并生成VHDL实体，确定类型 硬件组件的所有节点图形，从而生成对应的VHDL组件并在VHDL架构中写入关联信息，根据硬件组件图的边缘生成VHDL组件的相应信号连接，并将VHDL实体和体系结构输出到文件 以文本形式。

    Hardware component graph to hardware description language translation method
    2.
    发明申请
    Hardware component graph to hardware description language translation method 失效
    硬件组件图到硬件描述语言翻译方法

    公开(公告)号：US20070157147A1

    公开(公告)日：2007-07-05

    申请号：US11440065

    申请日：2006-05-25

    申请人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

    发明人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.

    摘要翻译： 一种HCG到HDL的翻译方法，可以自动生成VHDL代码。 该方法读取硬件组件图（HCG）以找到起始节点并获取起始节点的相应硬件组件子图，分析起始节点的所有信息，从而添加输入和输出组件并生成VHDL实体，确定类型 硬件组件的所有节点图形，从而生成对应的VHDL组件并在VHDL架构中写入关联信息，根据硬件组件图的边缘生成VHDL组件的相应信号连接，并将VHDL实体和体系结构输出到文件 以文本形式。

    Method of automatic synthesis of sequential quantum Boolean circuits
    3.
    发明授权
    Method of automatic synthesis of sequential quantum Boolean circuits 失效
    自动合成顺序量子布尔电路的方法

    公开(公告)号：US07398507B2

    公开(公告)日：2008-07-08

    申请号：US11430987

    申请日：2006-05-10

    申请人： Li-Kai Chang ,  Fu-Chiung Cheng

    发明人： Li-Kai Chang ,  Fu-Chiung Cheng

    IPC分类号： G06F17/50

    CPC分类号： B82Y10/00 ,  G06N99/002

    摘要： A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an integer; (B) determining whether the state graph is reversible; (C) encoding the M state nodes by using a unique state encoding when step (B) decides that the state graph is reversible, and producing a unique state coding reversible state graph; (D) transferring the unique state coding reversible state graph (USCRSG) into a corresponding self-timed transformation graph; (E) performing a state decomposition on the self-timed transformation graph and producing a decomposed self-timed transformation graph; and (F) constructing a quantum Boolean circuit of the decomposed self-timed transformation graph.

    摘要翻译： 一种自动合成顺序量子布尔电路的方法，用于将自定时电路传送到顺序量子布尔电路中，并合成顺序量子布尔电路，其包括以下步骤：（A）将自定时电路传送到状态图 具有M个状态节点，其中M是整数; （B）确定状态图是否可逆; （C）当步骤（B）判定状态图是可逆的时，通过使用唯一状态编码对M个状态节点进行编码，并产生唯一的状态编码可逆状态图; （D）将唯一状态编码可逆状态图（USCRSG）转移到相应的自定时变换图中; （E）对自适应变换图进行状态分解并产生分解的自时变换图; 和（F）构建分解的自定时变换图的量子布尔电路。

    Process of automatically translating a high level programming language into an extended activity diagram
    4.
    发明申请
    Process of automatically translating a high level programming language into an extended activity diagram 审中-公开
    自动将高级编程语言翻译成扩展活动图的过程

    公开(公告)号：US20070169054A1

    公开(公告)日：2007-07-19

    申请号：US11471485

    申请日：2006-06-21

    申请人： Fu-Chiung Cheng ,  Kuan-Yu Yan ,  Jian-Yi Chen ,  Shu-Ming Chang ,  Ping-Yun Wang ,  Li-Kai Chang ,  Chin-Tai Chou ,  Ming-Shiou Chiang

    发明人： Fu-Chiung Cheng ,  Kuan-Yu Yan ,  Jian-Yi Chen ,  Shu-Ming Chang ,  Ping-Yun Wang ,  Li-Kai Chang ,  Chin-Tai Chou ,  Ming-Shiou Chiang

    IPC分类号： G06F9/45

    CPC分类号： G06F8/74

    摘要： A process of automatically translating a high level programming language into an extended activity diagram (EAD), which can translate source codes coded by the high level programming language into a corresponding activity diagram (AD) before the high level language is translated into a hardware description language (HDL). The process adds a new translation rule in a compiler and modifies the AD specification of a unified modeling language (UML) to accordingly translate the source codes into the AD and present the programming logic and executing flow of the source codes in a visualization form. In addition, the process can translate the high level programming language into a unified format for representation, and the AD can benefit simulation and requirement in a following HDL translation.

    摘要翻译： 将高级编程语言自动翻译成扩展活动图（EAD）的过程，其可以在将高级语言转换为硬件描述之前将由高级编程语言编码的源代码转换为相应的活动图（AD） 语言（HDL）。 该过程在编译器中添加了一个新的翻译规则，并修改了统一建模语言（UML）的AD规范，从而将源代码转换为AD，并呈现编程逻辑，并以可视化形式执行源代码的流程。 此外，该过程可以将高级编程语言转换为统一的表示格式，AD可以在以下HDL翻译中受益于仿真和要求。

    Method of automatic synthesis of sequential quantum Boolean circuits
    5.
    发明申请
    Method of automatic synthesis of sequential quantum Boolean circuits 失效
    自动合成顺序量子布尔电路的方法

    公开(公告)号：US20070266347A1

    公开(公告)日：2007-11-15

    申请号：US11430987

    申请日：2006-05-10

    申请人： Li-Kai Chang ,  Fu-Chiung Cheng

    发明人： Li-Kai Chang ,  Fu-Chiung Cheng

    IPC分类号： G06F17/50

    CPC分类号： B82Y10/00 ,  G06N99/002

    摘要： A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an integer; (B) determining whether the state graph is reversible; (C) encoding the M state nodes by using a unique state encoding when step (B) decides that the state graph is reversible, and producing a unique state coding reversible state graph; (D) transferring the unique state coding reversible state graph (USCRSG) into a corresponding self-timed transformation graph; (E) performing a state decomposition on the self-timed transformation graph and producing a decomposed self-timed transformation graph; and (F) constructing a quantum Boolean circuit of the decomposed self-timed transformation graph.

    摘要翻译： 一种自动合成顺序量子布尔电路的方法，用于将自定时电路传送到顺序量子布尔电路中，并合成顺序量子布尔电路，其包括以下步骤：（A）将自定时电路传送到状态图 具有M个状态节点，其中M是整数; （B）确定状态图是否可逆; （C）当步骤（B）判定状态图是可逆的时，通过使用唯一状态编码对M个状态节点进行编码，并产生唯一的状态编码可逆状态图; （D）将唯一状态编码可逆状态图（USCRSG）转移到相应的自定时变换图中; （E）对自适应变换图进行状态分解并产生分解的自时变换图; 和（F）构建分解的自定时变换图的量子布尔电路。