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    PSEUDO-DIGITAL AVERAGE SUB SAMPLING METHOD AND APPARATUS
    1.
    发明申请
    PSEUDO-DIGITAL AVERAGE SUB SAMPLING METHOD AND APPARATUS 有权
    PSEUDO-DIGITAL AVERAGE子采样方法和设备

    公开(公告)号：US20120249824A1

    公开(公告)日：2012-10-04

    申请号：US13437361

    申请日：2012-04-02

    申请人： Yong LIM ,  Kyoung Min Koh ,  Soo Youn Kim

    发明人： Yong LIM ,  Kyoung Min Koh ,  Soo Youn Kim

    IPC分类号： G06K9/32 ,  H04N5/228

    CPC分类号： H03M1/56 ,  H03M1/1023 ,  H03M1/123 ,  H04N5/3575 ,  H04N5/378

    摘要： A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.

    摘要翻译： 一种k * k次采样的方法，其中k是大于1的整数，排列成行和列的多个像素的全帧读出，每个像素属于至少两组中的一个，第一组被配置为感测 图像参数的第一值和被配置为感测图像参数的第二值的第二组，所述方法包括对第一行中的至少一组的k个像素的信号进行采样，以输出二次采样的信号，将二次采样的信号转换为数字信号 具有比全帧读出更低的分辨率，对k行进行重复采样和转换，以及在至少一个集合内为第一至第k行添加数字信号。

    Analog to Digital Converters, Image Sensor Systems, and Methods of Operating the Same
    2.
    发明申请
    Analog to Digital Converters, Image Sensor Systems, and Methods of Operating the Same 有权
    模数转换器，图像传感器系统及其操作方法

    公开(公告)号：US20120113286A1

    公开(公告)日：2012-05-10

    申请号：US13270968

    申请日：2011-10-11

    申请人： Seung-Hyun LIM ,  Kwi-Sung YOO ,  Kyoung-Min KOH ,  Yu-Jin PARK ,  Chi-Ho HWANG ,  Yong LIM

    发明人： Seung-Hyun LIM ,  Kwi-Sung YOO ,  Kyoung-Min KOH ,  Yu-Jin PARK ,  Chi-Ho HWANG ,  Yong LIM

    IPC分类号： H04N5/228 ,  H03M1/12

    CPC分类号： H03M1/144 ,  H03M1/56 ,  H04N5/378

    摘要： An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

    摘要翻译： 模数转换器（ADC）可以包括多输入比较单元，其被配置为比较来自图像传感器的像素电压，包括在粗略操作模式期间修改的阶梯电压的比较电压和包括斜坡电压的斜坡电压 在精细操作模式下彼此修改，以提供指示与斜坡电压组合的比较电压是否大于或小于像素电压的比较结果信号。 选择控制信号生成单元可以接收比较结果信号和模式控制信号，以指示粗略或精细模式，以提供允许修改粗略模式中的比较电压并且保持比较电压恒定的选择控制信号 精细模式。 参考电压选择单元可以接收选择控制信号以控制比较电压的修改。

    Counter array and image sensor including the same
    3.
    发明授权
    Counter array and image sensor including the same 有权
    计数器阵列和图像传感器包括相同的

    公开(公告)号：US08115845B2

    公开(公告)日：2012-02-14

    申请号：US12320624

    申请日：2009-01-30

    申请人： Kyoung Min Koh ,  Kyung-Min Kim ,  Yong Lim

    发明人： Kyoung Min Koh ,  Kyung-Min Kim ,  Yong Lim

    IPC分类号： H04N3/14 ,  H04N5/335

    CPC分类号： H03K23/56 ,  H04N5/378

    摘要： A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.

    摘要翻译： 可以提供一种计数器阵列和包括该计数器阵列的图像传感器。 计数器阵列可以包括控制器和多个计数器单元。 控制器可以输出操作控制信号和方向指示信号。 计数器单元保持以前的输出值，或者可以响应于操作控制信号执行计数操作，并且可以在执行计数操作时响应于方向指示信号执行向上计数操作或递减计数操作。

    Clock divider
    4.
    发明授权
    Clock divider 有权
    时钟分频器

    公开(公告)号：US07424087B2

    公开(公告)日：2008-09-09

    申请号：US11609411

    申请日：2006-12-12

    申请人： Kyoung-Min Koh

    发明人： Kyoung-Min Koh

    IPC分类号： H03K21/00 ,  H03K23/00

    CPC分类号： H03K23/667 ,  H03K23/425

    摘要： A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in synchronization with a clock signal. The second state storage unit performs transition of a second state value in synchronization with a first state signal corresponding to the first state value. The first control signal generating unit generates a first control signal for determining a first state transition path based on a first division ratio control signal. The state update unit generates the update signal based on the first control signal and the first state signal. The output unit selectively output the first state signal or a second state signal corresponding to the second state value.

    摘要翻译： 时钟分频器包括第一状态存储单元，第二状态存储单元，第一控制信号生成单元，状态更新单元和输出单元。 第一状态存储单元接收与时钟信号同步地执行第一状态值的​​转换的更新信号。 第二状态存储单元与对应于第一状态值的​​第一状态信号同步地执行第二状态值的转换。 第一控制信号产生单元基于第一分频比控制信号产生用于确定第一状态转换路径的第一控制信号。 状态更新单元基于第一控制信号和第一状态信号生成更新信号。 输出单元选择性地输出与第二状态值对应的第一状态信号或第二状态信号。

    DC-DC converter utilizing a modified Schmitt trigger circuit and method of modulating a pulse width
    5.
    发明授权
    DC-DC converter utilizing a modified Schmitt trigger circuit and method of modulating a pulse width 有权
    使用改进的施密特触发电路的DC-DC转换器和调制脉冲宽度的方法

    公开(公告)号：US07417412B2

    公开(公告)日：2008-08-26

    申请号：US11369799

    申请日：2006-03-07

    申请人： Kyoung-Min Koh

    发明人： Kyoung-Min Koh

    IPC分类号： G05F1/40

    CPC分类号： H02M3/1563

    摘要： A DC-DC converter includes a PWM modulator, a power switch and a filter. The PWM modulator positively feeds back a pulse width modulated signal of which a pulse width and a frequency are varied to generate an oscillated signal, amplifies a difference between a negatively fed-back direct current output signal and a reference signal to output a first signal, and compares the first signal with the oscillated signal to generate first and second switching signals. The power switch transfers an input signal to a first output node in response to the first and second switching signals, and generates the pulse width modulated signal, wherein the pulse width modulated signal is provided to the first output node. The filter generates a direct current output voltage signal in response to the pulse width modulated signal, wherein the direct current output voltage signal is provided to a second output node.

    摘要翻译： DC-DC转换器包括PWM调制器，电源开关和滤波器。 PWM调制器正向反馈脉冲宽度和频率变化的脉宽调制信号以产生振荡信号，放大负反馈直流输出信号和参考信号之间的差以输出第一信号， 并且将第一信号与振荡信号进行比较以产生第一和第二开关信号。 电源开关响应于第一和第二开关信号将输入信号传送到第一输出节点，并产生脉宽调制信号，其中脉冲宽度调制信号被提供给第一输出节点。 滤波器响应于脉宽调制信号产生直流输出电压信号，其中直流输出电压信号被提供给第二输出节点。

    Multiple Data Rate Counter, Data Converter including the Same, and Image Sensor Including the Same
    8.
    发明申请
    Multiple Data Rate Counter, Data Converter including the Same, and Image Sensor Including the Same 审中-公开
    多数据速率计数器，包括它的数据转换器和包括它的图像传感器

    公开(公告)号：US20150129748A1

    公开(公告)日：2015-05-14

    申请号：US14602377

    申请日：2015-01-22

    申请人： Kyung-min Kim ,  Kyoung-min Koh ,  Yoon-seok Han

    发明人： Kyung-min Kim ,  Kyoung-min Koh ,  Yoon-seok Han

    IPC分类号： H03K23/50 ,  H04N5/378 ,  H03K21/10

    CPC分类号： H03K23/50 ,  H03K21/10 ,  H03K23/58 ,  H04N5/378

    摘要： A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

    摘要翻译： 计数器包括一个缓冲单元和一个纹波计数器。 缓冲单元通过缓冲至少一个时钟信号直到终止时间点来产生计数的至少一个最低有效信号。 纹波计数器通过响应于至少一个最低有效信号顺序切换来产生计数的至少一个最高有效信号。 计数器可以提高操作速度和降低功耗，从而实现多种数据速率计数。

    IMAGE SENSOR AND METHOD OF DRIVING THE SAME
    9.
    发明申请
    IMAGE SENSOR AND METHOD OF DRIVING THE SAME 有权
    图像传感器及其驱动方法

    公开(公告)号：US20150034803A1

    公开(公告)日：2015-02-05

    申请号：US14446417

    申请日：2014-07-30

    申请人： Kyoung-Min KOH ,  Kwang-Hyun LEE ,  Ju-Ha KIM ,  Han YANG ,  Jae-Cheol YUN

    发明人： Kyoung-Min KOH ,  Kwang-Hyun LEE ,  Ju-Ha KIM ,  Han YANG ,  Jae-Cheol YUN

    IPC分类号： H04N5/361

    CPC分类号： H04N5/361

    摘要： Provided are an image sensor and a method of driving the same. The image sensor includes n optical black pixels which are arranged in the same horizontal line; and m comparators which are matched with the n optical black pixels, wherein n is a natural number greater than or equal to two, and m is a natural number greater than n.

    摘要翻译： 提供一种图像传感器及其驱动方法。 图像传感器包括布置在相同水平线上的n个光学黑色像素; 和与n个光学黑色像素匹配的m个比较器，其中n是大于或等于2的自然数，m是大于n的自然数。