公开(公告)号：US20050246513A1

公开(公告)日：2005-11-03

申请号：US11117326

申请日：2005-04-29

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： F02D45/00 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F12/0246 ,  G06F12/0638

摘要： A microcomputer has flash memory having at least two data areas, others of which can be written while one is being read, and substitute RAM which is used when adjusting control data prior to adjustment (pre-adjustment control data) which is stored in for example one of the data areas; the CPU controls equipment to be controlled by executing a program in a program storage portion using control data in one of the data areas. In adjustment processing of the control data, the control data in one of the data areas is copied to RAM and adjusted to values appropriate to the equipment to be controlled, and the adjusted control data is written to another data area, after which the addresses in a memory map of the two data areas are swapped. Subsequently, the CPU controls the equipment using the adjusted control data which physically is stored in the other data area.

摘要翻译： 微型计算机具有至少两个数据区域的闪速存储器，其中一个可以在读取时被写入，并且替换当在例如存储的调整之前调整控制数据时使用的RAM（预调节控制数据） 数据区之一; CPU通过使用数据区域之一中的控制数据在程序存储部分中执行程序来控制要控制的设备。 在控制数据的调整处理中，将一个数据区域中的控制数据复制到RAM中，并将其调整为适合要控制的设备的值，并将调整后的控制数据写入另一个数据区域，之后将其中的地址 交换两个数据区的存储器映射。 随后，CPU使用物理地存储在另一数据区中的经调整的控制数据来控制设备。

公开(公告)号：US5625598A

公开(公告)日：1997-04-29

申请号：US575474

申请日：1995-12-20

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C11/413 ,  G11C7/12

摘要： A semiconductor device has a precharge control circuit for generating a precharge control signal, the precharge control signal being at an active level when all word lines do not indicate a high level and being at an inactive level when an access control signal (read control signal or write control signal) is input to the precharge control circuit for controlling a precharge circuit for precharging bit lines to a predetermined voltage.

摘要翻译： 半导体器件具有用于产生预充电控制信号的预充电控制电路，当所有字线在存取控制信号（读取控制信号或读取控制信号）时所有字线不指示高电平并处于非活动电平时，预充电控制信号处于有效电平 写入控制信号）输入到预充电控制电路，用于控制用于将位线预充电到预定电压的预充电电路。

公开(公告)号：US08279672B2

公开(公告)日：2012-10-02

申请号：US12656177

申请日：2010-01-20

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/28

摘要： A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing.

摘要翻译： 非易失性存储器包括存储块，每个存储块包括用于存储用户数据的数据存储区域和一对一地提供以对应于每个数据存储区域的鉴别区域，并存储指示写入状态的判别数据 数据到数据存储区域。 非易失性存储器还包括控制电路，其根据各个存储块的识别数据之间的相对差异关系确定将成为用户数据的存储目的地的数据存储区域，并且改变对应的鉴别区域的鉴别数据 到写入用户数据的数据存储区域与写入之前不同的值。

公开(公告)号：US20100182836A1

公开(公告)日：2010-07-22

申请号：US12656177

申请日：2010-01-20

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/28

摘要： A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing.

摘要翻译： 非易失性存储器包括存储块，每个存储块包括用于存储用户数据的数据存储区域和一对一地提供以对应于每个数据存储区域的鉴别区域，并存储指示写入状态的判别数据 数据到数据存储区域。 非易失性存储器还包括控制电路，其根据各个存储块的识别数据之间的相对差异关系确定将成为用户数据的存储目的地的数据存储区域，并且改变对应的鉴别区域的鉴别数据 到写入用户数据的数据存储区域与写入之前不同的值。

公开(公告)号：US20090168550A1

公开(公告)日：2009-07-02

申请号：US12318105

申请日：2008-12-22

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G06F13/4072

摘要： An output port circuit includes a plurality of output buffers; a plurality of first holding circuits configured to hold output data to be outputted to the plurality of output buffers; a plurality of second holding circuits configured to hold output data to be outputted to the plurality of first holding circuits; and a plurality of third holding circuits configured to hold bit pattern data for individually setting whether the output data of the plurality of second holding circuits are latched by the plurality of first holding circuits. Data input to the plurality of second holding circuits and data input to the plurality of third holding circuits are controlled at a same timing.

摘要翻译： 输出端口电路包括多个输出缓冲器; 多个第一保持电路，被配置为保持要输出到多个输出缓冲器的输出数据; 多个第二保持电路，被配置为保持要输出到多个第一保持电路的输出数据; 以及多个第三保持电路，被配置为保持用于单独设置多个第二保持电路的输出数据是否被多个第一保持电路锁存的位模式数据。 输入到多个第二保持电路的数据和输入到多个第三保持电路的数据在相同的定时被控制。

公开(公告)号：US5834949A

公开(公告)日：1998-11-10

申请号：US757998

申请日：1996-11-27

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G06F3/00 ,  G06F11/22 ,  H04L25/02 ,  H03K19/0185

CPC分类号： H04L25/028 ,  H04L25/0292

摘要： The invention provides a bus driver failure detection system which facilitates detection of a failure of a bus driver from which data are sent out to a bus. The bus driver failure detection system includes a plurality of bus drivers for sending out signals to a single bus, at least one receiver connected to the bus, and an impedance control circuit for controlling the bus so that, upon testing, the bus does not exhibit a high impedance state. The impedance control circuit may be constructed as a circuit which holds a value of the bus in response to a test signal.

摘要翻译： 本发明提供了一种总线驱动器故障检测系统，其有助于检测从总线驱动器发送数据到总线的故障。 总线驱动器故障检测系统包括用于向单个总线发送信号的多个总线驱动器，连接到总线的至少一个接收器和用于控制总线的阻抗控制电路，使得在测试时总线不显示 高阻抗状态。 阻抗控制电路可以被构造为响应于测试信号而保持总线的值的电路。

公开(公告)号：US06745278B2

公开(公告)日：2004-06-01

申请号：US09753112

申请日：2001-01-02

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G06F1200

CPC分类号： G06F9/4406 ,  G06F8/60

摘要： There is provided a computer that can safely rewrite any one of the areas where a boot program is stored with fewer actions in the self-mode. A nonvolatile memory is divided into a plurality of areas, each of which is separately erasable and includes a user area and a boot area designation flag indicating whether the corresponding user area is specified as a boot area. An area designation flag specifies the user area containing a boot program among a plurality of user areas. A CPU sets the value of the area designation flag based on the values of a plurality of boot area designation flags. When a system is started, the user area including the program for starting the operation of the CPU is determined based on the value of the area designation flag.

摘要翻译： 提供了一种计算机，其可以安全地重写存储引导程序的任何一个区域，而在自我模式中具有较少的动作。 非易失性存储器被划分为多个区域，每个区域是可单独擦除的，并且包括用户区域和指示对应的用户区域是否被指定为引导区域的引导区域指定标志。 区域指定标志指定在多个用户区域中包含引导程序的用户区域。 CPU根据多个引导区域指定标志的值来设定区域指定标志的值。 当系统启动时，基于区域指定标志的值确定包括用于开始CPU的操作的程序的用户区域。

公开(公告)号：US06046965A

公开(公告)日：2000-04-04

申请号：US157534

申请日：1998-09-21

申请人： Kaori Oba

发明人： Kaori Oba

IPC分类号： G06F1/14 ,  G04F1/00 ,  G06F1/06 ,  G06F9/48 ,  G04B23/02 ,  G04C21/00 ,  H03K3/02

CPC分类号： G04F1/005 ,  G06F1/06

摘要： A coincidence signal is output when coincidence of a timer counter with the set value of a comparison register is detected by a coincidence detecting circuit and the coincidence signal is input to the external CPU as an interruption signal to execute a CPU to start an interruption routine. In the interruption routine, a reverse enable flag is set, a flag indicating permission to reverse an output signal when the value of a key counter is larger than the value of a buzzer counter and a reverse enable flag is set, a flag indicating prohibition of reversing the output signal when the value of the key counter is smaller than that of the buzzer counter.

摘要翻译： 当一个定时器计数器与比较寄存器的设定值的一致性由一致检测电路检测到并且一致信号被输入到外部CPU作为中断信号以执行CPU以启动中断程序时，输出符合信号。 在中断程序中，设置反向使能标志，指示当密钥计数器的值大于蜂鸣器计数器的值和反向使能标志时反转输出信号的允许的标志，指示禁止 当键计数器的值小于蜂鸣器计数器的值时，反转输出信号。