Method and apparatus for modulating symbols in an orthogonal frequency division multiplexing system and transmission apparatus using the same
    2.
    发明授权
    Method and apparatus for modulating symbols in an orthogonal frequency division multiplexing system and transmission apparatus using the same 有权
    用于在正交频分复用系统中调制符号的方法和装置及使用其的发送装置

    公开(公告)号:US08046398B2

    公开(公告)日:2011-10-25

    申请号:US11966249

    申请日:2007-12-28

    CPC classification number: H04L27/2607 H04L5/0007 H04L27/263

    Abstract: A method for modulating a symbol in a transmitter of an Orthogonal Frequency Division Multiplexing (OFDM) system. The symbol modulation method includes multiplying an input stream of an Inverse Fast Fourier Transform (IFFT) unit by a Twiddling factor for circular-shifting the input stream of the IFFT unit by a Cyclic Prefix (CP) length; performing IFFT on the input stream of the IFFT unit, which is multiplied by the Twiddling factor; buffering data corresponding to the CP length beginning from a front of an output stream of the IFFT unit; and generating an OFDM symbol by forward-copying the buffered data to a back of the output stream of the IFFT unit.

    Abstract translation: 一种用于调制正交频分复用(OFDM)系统的发射机中的符号的方法。 符号调制方法包括将快速傅里叶逆变换(IFFT)单位的输入流乘以Twiddling因子,以便将IFFT单元的输入流循环移位循环前缀(CP)长度; 对IFFT单元的输入流执行IFFT,乘以Twiddling因子; 从IFFT单元的输出流的前面开始缓冲对应于CP长度的数据; 以及通过将所缓冲的数据转发到所述IFFT单元的输出流的背面来产生OFDM符号。

    Built-in dual band antenna device and operating method thereof in a mobile terminal

    公开(公告)号:US06452556B1

    公开(公告)日:2002-09-17

    申请号:US09956654

    申请日:2001-09-20

    Abstract: Disclosed are a built-in dual band antenna device and an operating method thereof in a mobile terminal. In the built-in antenna dual band antenna device, a built-in dual band antenna has a first conductive antenna pattern formed on a board extended from the upper side of a main PCB and a second conductive antenna pattern on a board extended at a right angle from the upper side of the main PCB. A whip antenna is connected to the built-in dual band antenna, and contained in the mobile terminal when the whip antenna is retracted. A whip antenna driver extends or retracts the whip antenna. A duplexer separates an RF signal received from the built-in dual band antenna from an RF signal to be transmitted to the built-in dual band antenna. A controller processes the RF signals received at and transmitted from the duplexer and controls the whip antenna driver to extend the whip antenna in a speech state or upon a call attempt from a user.

    Method and apparatus for reducing digital to analog conversion (DAC) bits in frequency division multiple access (FDMA) system
    4.
    发明授权
    Method and apparatus for reducing digital to analog conversion (DAC) bits in frequency division multiple access (FDMA) system 失效
    用于减少频分多址(FDMA)系统中的数模转换(DAC)位的方法和装置

    公开(公告)号:US08493954B2

    公开(公告)日:2013-07-23

    申请号:US12337702

    申请日:2008-12-18

    Abstract: A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.

    Abstract translation: 用于减少频分多址(FDMA)系统的发射机处的数模转换(DAC)比特的方法和装置减少了用于转换的比特数,以节省功率并降低操作成本。 该方法可以包括使用子载波分配信息,所需的信噪比(SNR)和峰均功率比(PAPR)来产生数字信号增益控制值和模拟信号增益控制值; 使用数字信号增益控制值控制输入到数模转换器的信号的增益; 使用数模转换器将受控增益的数字信号转换为模拟信号; 以及通过使用模拟信号增益控制值控制从数模转换器输出的信号的增益来恢复原始信号。

    Built-in single band antenna device and operating method thereof in mobile terminal
    6.
    发明授权
    Built-in single band antenna device and operating method thereof in mobile terminal 失效
    内置单频天线装置及其在移动终端中的操作方法

    公开(公告)号:US06885346B2

    公开(公告)日:2005-04-26

    申请号:US09956691

    申请日:2001-09-20

    CPC classification number: H01Q9/0421 H01Q1/244 H01Q9/30 H01Q21/28

    Abstract: There is provided a built-in single band antenna device and an operating method thereof in a mobile terminal. In the built-in antenna single band antenna device, a built-in single band antenna is formed into a conductive pattern on a board extended from the upper side of a main PCB. A whip antenna is connected to the built-in single band antenna, and contained in the mobile terminal when the whip antenna is retracted. A whip antenna driver extends or retracts the whip antenna. A duplexer separates an RF signal received from the built-in single band antenna from an RF signal to be transmitted to the built-in single band antenna. A controller processes the RF signals received at and transmitted from the duplexer and controls the whip antenna driver to extend the whip antenna in a speech state or upon a call attempt from a user.

    Abstract translation: 在移动终端中提供了内置的单频带天线装置及其操作方法。 在内置天线单频天线装置中,内置单频带天线形成为从主PCB的上侧延伸的板上的导电图案。 鞭状天线连接到内置的单频带天线,并且当鞭状天线缩回时包含在移动终端中。 鞭状天线驱动器延伸或缩回鞭状天线。 双工器将从内置单频带天线接收的RF信号与要发送到内置单频天线的RF信号分离。 控制器处理在双工器处接收和发送的RF信号,并且控制鞭状天线驱动器以语音状态或来自用户的呼叫尝试来延长鞭状天线。

    METHOD AND APPARATUS FOR REDUCING DIGITAL TO ANALOG CONVERSION (DAC) BITS IN FREQUENCY DIVISION MULTIPLE ACCESS (FDMA) SYSTEM
    9.
    发明申请
    METHOD AND APPARATUS FOR REDUCING DIGITAL TO ANALOG CONVERSION (DAC) BITS IN FREQUENCY DIVISION MULTIPLE ACCESS (FDMA) SYSTEM 失效
    用于减少频分多址(FDMA)系统中数字到模拟转换(DAC)位的方法和装置

    公开(公告)号:US20090154442A1

    公开(公告)日:2009-06-18

    申请号:US12337702

    申请日:2008-12-18

    Abstract: A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.

    Abstract translation: 用于减少频分多址(FDMA)系统的发射机处的数模转换(DAC)比特的方法和装置减少了用于转换的比特数,以节省功率并降低操作成本。 该方法可以包括使用子载波分配信息,所需的信噪比(SNR)和峰均功率比(PAPR)来产生数字信号增益控制值和模拟信号增益控制值; 使用数字信号增益控制值控制输入到数模转换器的信号的增益; 使用数模转换器将受控增益的数字信号转换为模拟信号; 以及通过使用模拟信号增益控制值控制从数模转换器输出的信号的增益来恢复原始信号。

    APPARATUS AND METHOD FOR BLOCK INTERLEAVING IN MOBILE COMMUNICATION SYSTEM
    10.
    发明申请
    APPARATUS AND METHOD FOR BLOCK INTERLEAVING IN MOBILE COMMUNICATION SYSTEM 审中-公开
    移动通信系统中的块交织的装置和方法

    公开(公告)号:US20090083514A1

    公开(公告)日:2009-03-26

    申请号:US12234788

    申请日:2008-09-22

    Abstract: A method and apparatus for block interleaving that eliminates the step of intermediary buffering. The method includes: (a) calculating a memory address at which first output data, of which number is equal to the number of rows of a first encoder is stored, (b) storing the first output data at the calculated memory address of a circular buffer, (c) storing second output data at an address which is incremented by a specific constant value from the calculated memory address of the circular buffer, and (d) storing (n+1)th output data at an address which is incremented by n from the calculated memory address of the circular buffer.

    Abstract translation: 一种用于块交织的方法和装置,其消除了中间缓冲的步骤。 该方法包括:(a)计算存储器地址,在该存储器地址处,存储第一个输出数据的数量等于第一个编码器的行数,(b)将第一个输出数据存储在计算的循环存储器地址 缓冲器,(c)将存储第二输出数据存储在从计算的循环缓冲器的存储器地址中增加特定常数值的地址处,以及(d)将第(n + 1)个输出数据存储在增加了 n从循环缓冲区的计算内存地址。

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