公开(公告)号：US06388993B1

公开(公告)日：2002-05-14

申请号：US09095744

申请日：1998-06-11

申请人： Jae-Jin Shin ,  Kyung-Geun Lee ,  Dan-Keun Sung ,  Jeong-Won Heo ,  Sung-Hyuk Byun ,  Ju-Yong Lee ,  Jin-Woo Yang

发明人： Jae-Jin Shin ,  Kyung-Geun Lee ,  Dan-Keun Sung ,  Jeong-Won Heo ,  Sung-Hyuk Byun ,  Ju-Yong Lee ,  Jin-Woo Yang

IPC分类号： G06F1100

CPC分类号： H04L49/9047 ,  H04L47/50 ,  H04L47/6215 ,  H04L49/3018 ,  H04L49/506 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9078 ,  H04L2012/5635 ,  H04L2012/5682

摘要： An ATM switch having the buffer threshold controller to control the cell input into the switching element using the back-pressure signal and a method for determining the buffer threshold according to the buffer threshold controller are disclosed. The ATM switch includes buffer pool storing the cell input to the switch; buffer pool control part storing the buffer pool occupancy information per input port of the buffer pool; threshold control part receiving the buffer pool occupancy information from the buffer pool control part and calculating the threshold per input port periodically and then sending it to the buffer pool control part; input crosspoint control part controlling the cells input to the buffer pool by receiving the control signal from the buffer pool control part; and output crosspoint control part controlling the cells output from the buffer pool by receiving the control signal from the buffer pool control part. The method includes the steps of calculating ri, the buffer pool occupancy rate of the ith input port (i=1, 2, 3, . . . , N); calculating rH, the threshold of the buffer pool occupancy rate of the ith input port; calculating Li, the number of occupation of the cells in the buffer pool of the ith input port; calculating the difference, Dorder(k)=tj−Lj(k=1, 2, 3, N . . . , N) between tj, the threshold of the jth input port and Lj, the number of cells stored in the buffer pool, where i≠j (j=1, 2, 3, . . . , N); calculating tD—order(k), the threshold in case where the tj−Lj is the kth value in descending order from the N input ports; calculating bD—order(k), minimum threshold to guarantee the minimum cell input; and comparing &Dgr;, the minimum unit of increase or decrease of the threshold and the value of tD—order(k)−bD—order(k).

摘要翻译： 公开了具有缓冲器阈值控制器的ATM开关，其使用背压信号来控制对开关元件的输入，以及根据缓冲器阈值控制器确定缓冲器阈值的方法。 ATM交换机包括存储单元输入到交换机的缓冲池; 缓冲池控制部分，每个缓冲池的每个输入端口存储缓冲池占用信息; 阈值控制部分从缓冲池控制部分接收缓冲池占用信息，周期性地计算每个输入端口的阈值，然后发送给缓冲池控制部分; 输入交叉点控制部分，通过从缓冲池控制部分接收控制信号来控制输入到缓冲池的单元; 并通过从缓冲池控制部分接收控制信号，输出控制从缓冲池输出的单元的交叉点控制部分。 该方法包括以下步骤：计算第i个输入端口的缓冲池占用率（i = 1,2,3，...，N）; 计算rH，第i个输入端口的缓冲池占用率的阈值; 计算Li，第i个输入端口的缓冲池中的单元的占用次数; 在第j个输入端口和Lj的阈值之间计算差值，Dorder（k）= tj-Lj（k = 1,2,3，N ...，N），存储在缓冲池中的单元数 ，其中i <> j（j = 1,2,3，...，N）; 在从N个输入端口降序的情况下计算tD-order（k），tj-Lj是第k个值的阈值; 计算bD阶（k），最小阈值以保证最小单元格输入; 并比较DELTA，阈值的增加或减小的最小单位和tD阶（k）-bD阶（k）的值。

公开(公告)号：US06259698B1

公开(公告)日：2001-07-10

申请号：US09095727

申请日：1998-06-11

申请人： Jae-Jin Shin ,  Kyung-Geun Lee ,  Dan-Keun Sung ,  Jeong-Won Heo ,  Sung-Hyuk Byun ,  Ju-Yong Lee ,  Jin-Woo Yang

发明人： Jae-Jin Shin ,  Kyung-Geun Lee ,  Dan-Keun Sung ,  Jeong-Won Heo ,  Sung-Hyuk Byun ,  Ju-Yong Lee ,  Jin-Woo Yang

IPC分类号： H04H1228

CPC分类号： H04L49/506 ,  H04L29/06 ,  H04L49/15 ,  H04L49/25 ,  H04L49/255 ,  H04L49/3018 ,  H04L49/3081 ,  H04L49/90 ,  H04L2012/5651 ,  H04L2012/5682

摘要： A controller for the logical buffer depth in ATM switching system and a method for determining the logical queue depth, using the back-pressure signal and the occupied buffer depth information and supporting the P classes, are disclosed. The controller includes Routing Table Element making tag for routing of input cell; Input Buffer storing the cell that a tag is attached to in said routing table element; Switch fabric that reads the cell from said input buffer and then switches it to the output port; and Input buffer controller controlling the logical queue size in said input buffer. And the method for determining the logical queue depth includes the steps of calculating the back-pressure signal occurrence rate bi of the ith class; calculating the back-pressure signal occurrence threshold rate bi—th of the ith class; calculating the buffer depth Ti of the logical queue of the ith class; calculating threshold values TiH, TiL of the two buffer depths of the ith class; calculating the buffer size Li of the logical queue of the ith class; calculating the empty area size Dj(j=1, 2, 3, L, P) of logical queues for the number of p classes.

摘要翻译： 公开了一种用于ATM交换系统中的逻辑缓冲器深度的控制器以及使用背压信号和占用缓冲器深度信息并支持P类来确定逻辑队列深度的方法。 控制器包括用于路由输入单元的路由表元素制作标签; 输入缓冲器，存储所述路由表元素中附加标签的单元; 交换结构，从所述输入缓冲区读取单元，然后将其切换到输出端口; 以及控制所述输入缓冲器中的逻辑队列大小的输入缓冲器控制器。 并且用于确定逻辑队列深度的方法包括计算第i类的背压信号发生率bi的步骤; 计算第i类的背压信号发生阈值率第二; 计算第i类逻辑队列的缓冲区深度Ti; 计算第i类的两个缓冲深度的阈值TiH，TiL; 计算第i类逻辑队列的缓冲区大小Li; 计算p类的数量的逻辑队列的空区域大小Dj（j = 1,2,3，L，P）。

公开(公告)号：US6023469A

公开(公告)日：2000-02-08

申请号：US874822

申请日：1997-06-13

申请人： Dan-Keun Sung ,  Kyeong-Ho Lee ,  Soo-Jong Lee ,  Tae-Won Kim ,  Jeong-Won Heo ,  Sung-Hyuk Byun ,  Ju-Yong Lee

发明人： Dan-Keun Sung ,  Kyeong-Ho Lee ,  Soo-Jong Lee ,  Tae-Won Kim ,  Jeong-Won Heo ,  Sung-Hyuk Byun ,  Ju-Yong Lee

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/937 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04Q11/0478 ,  H04L2012/5647 ,  H04L2012/5681

摘要： An idle address controller for a shared buffer type ATM switch controls the addresses of output cells in a common memory to be stored directly in an idle address buffer without passing through the conventional idle address delay controller, by improving the idle address control scheme of a unit switch. The idle address controller includes an idle address control signal generator for generating idle address control signals based on the buffer length information from counters, idle address control signal buffers for storing the idle address control signals, and an idle address control signal multiplexer. Therefore, the idle addresses can be efficiently provided, and this mechanism lowers cell loss and reduces required memory capacity.

摘要翻译： 用于共享缓冲型ATM交换机的空闲地址控制器通过改进单元的空闲地址控制方案来控制公共存储器中的输出单元的地址，以直接存储在空闲地址缓冲器中，而不经过常规的空闲地址延迟控制器 开关。 空闲地址控制器包括用于基于来自计数器的缓冲器长度信息产生空闲地址控制信号的空闲地址控制信号发生器，用于存储空闲地址控制信号的空闲地址控制信号缓冲器和空闲地址控制信号多路复用器。 因此，可以有效地提供空闲地址，并且这种机制降低了信元丢失并减少了所需的存储容量。