公开(公告)号：US07129952B2

公开(公告)日：2006-10-31

申请号：US10176398

申请日：2002-06-21

申请人： Ruen-Rone Lee ,  Chien-Chung Hsiao ,  Lin-Tien Mei ,  Hung-Ta Pai

发明人： Ruen-Rone Lee ,  Chien-Chung Hsiao ,  Lin-Tien Mei ,  Hung-Ta Pai

IPC分类号： G06F13/14 ,  G06F15/16

CPC分类号： G06T15/005 ,  G06F3/14 ,  G06T2210/52 ,  G09G3/003 ,  G09G5/363 ,  G09G2350/00 ,  G09G2360/06

摘要： A core logic circuit which works with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller for receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command that is processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

摘要翻译： 提供了与计算机系统中的CPU和主图形加速器一起工作的核心逻辑电路。 核心逻辑芯片包括电连接到CPU的主机控制器，用于从CPU接收命令; 电连接到主机控制器的辅助图形引擎，用于接收和处理命令; 电连接到辅助图形引擎的传输控制器，用于将由辅助图形引擎处理和输出的命令发送到主图形加速器以进一步处理。

公开(公告)号：US06804758B2

公开(公告)日：2004-10-12

申请号：US09895604

申请日：2001-06-29

申请人： Ming-Hao Liao ,  Hung-Ta Pai

发明人： Ming-Hao Liao ,  Hung-Ta Pai

IPC分类号： G06F1200

CPC分类号： G06F13/1642

摘要： In a method for adaptive arbitration of requests for accessing a memory unit in a multi-stage pipeline engine that includes a plurality of request queues corresponding to the stages of the pipeline engine, each of the request queues is assigned to one of a high-priority group and a low-priority group in accordance with an operating state of the memory unit. The request queues in the high-priority group are then processed prior to the request queues in the low-priority group.

摘要翻译： 在包括对应于流水线引擎的各级的多个请求队列的多级流水线引擎中访问存储单元的请求的自适应仲裁的方法中，将每个请求队列分配给高优先级中的一个 组和低优先级组，根据存储器单元的操作状态。 然后在低优先级组中的请求队列之前处理高优先级组中的请求队列。

公开(公告)号：US06882753B2

公开(公告)日：2005-04-19

申请号：US09874559

申请日：2001-06-04

申请人： Cheng-Hsien Chen ,  Chen-Yi Lee ,  Lin-Tien Mei ,  Hung-Ta Pai

发明人： Cheng-Hsien Chen ,  Chen-Yi Lee ,  Lin-Tien Mei ,  Hung-Ta Pai

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  G06K9/46

CPC分类号： G06T9/007 ,  H04N19/124 ,  H04N19/152 ,  H04N19/17 ,  H04N19/192 ,  H04N19/48 ,  H04N19/60

摘要： A method is adapted for compressing an image data block, and includes the steps of: (a) subjecting the image data block to discrete cosine transformation so as to generate discrete cosine transform data; (b) quantizing the discrete cosine transform data in accordance with a quantizer matrix that consists of an array of quantizing coefficients so as to generate quantized data; (c) encoding the quantized data using an entropy coding algorithm so as to generate an encoded bitstream; and (d) when the length of the encoded bitstream does not fall within a predetermined range, adjusting the quantizing coefficients in the quantizer matrix and repeating steps (b) and (c) until the length of the encoded bitstream falls within the predetermined range.

摘要翻译： 一种适于压缩图像数据块的方法，包括以下步骤：（a）对图像数据块进行离散余弦变换，以产生离散余弦变换数据; （b）根据由量化系数阵列组成的量化器矩阵量化离散余弦变换数据，以产生量化数据; （c）使用熵编码算法对所述量化数据进行编码，以便生成编码比特流; 和（d）当编码比特流的长度不落在预定范围内时，调整量化器矩阵中的量化系数并重复步骤（b）和（c），直到编码比特流的长度落在预定范围内。

公开(公告)号：US06583642B2

公开(公告)日：2003-06-24

申请号：US09930974

申请日：2001-08-17

申请人： Hung-Ju Huang ,  Chun-An Tu ,  Hung-Ta Pai

发明人： Hung-Ju Huang ,  Chun-An Tu ,  Hung-Ta Pai

IPC分类号： G01R3126

CPC分类号： G01R31/31922 ,  G01R31/3187

摘要： An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

公开(公告)号：US06407595B1

公开(公告)日：2002-06-18

申请号：US09542938

申请日：2000-04-04

申请人： Hung-Ju Huang ,  Hung-Ta Pai

发明人： Hung-Ju Huang ,  Hung-Ta Pai

IPC分类号： H03B1900

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

摘要： A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

摘要翻译： 用于选通电路的时钟信号的数字时钟节流装置至少包括蓄电池和门控电路。 响应于节流值的累加器产生第一输出信号。 第一输出信号被分成具有最高有效位的节流信号和除了最高有效位之外的第一输出信号的休息位的反馈信号。 反馈信号被发送到累加器，用于累加到作为第一输出信号的节流值。 与节流器耦合的门控电路响应于节流信号和时钟信号，门控时钟信号的一些时钟周期，从而提供调节频率的门控时钟信号。

公开(公告)号：US20080120905A1

公开(公告)日：2008-05-29

申请号：US11942872

申请日：2007-11-20

申请人： Hung Ta Pai

发明人： Hung Ta Pai

IPC分类号： A01G9/02

CPC分类号： A01G9/027 ,  A01G9/28

摘要： A sectional-type raised garden bed structure includes a first wall section being provided at an end with at least one mortise, a second wall section being provided at an end with at least one tenon adapted to engage with the at least one mortise on the first wall section for connecting the first and the second wall section together. The tenon is flexible for the connected first and second wall sections to contain a predetermined angle therebetween according to actual need.

摘要翻译： 剖面式升花园床结构包括：第一壁段，其末端设置有至少一个榫眼;第二壁部分在端部设置有至少一个榫头，适于在第一壁面上与至少一个榫接合 用于将第一和第二壁部分连接在一起的壁部分。 根据实际需要，榫头对于连接的第一和第二壁部分是柔性的，以在其间包含预定的角度。

公开(公告)号：US06738945B2

公开(公告)日：2004-05-18

申请号：US09805621

申请日：2001-03-14

申请人： Hung-Ming Lin ,  Hung-Ta Pai

发明人： Hung-Ming Lin ,  Hung-Ta Pai

IPC分类号： H03M1300

CPC分类号： H03M13/091 ,  H03M13/098 ,  H04L25/4906

摘要： A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value, and outputting an indicating signal while the changed value is larger than a threshold, an encoder electrically connected to the detector for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and a decoder electrically connected to the detector and the encoder receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.

摘要翻译： 适用于发送n位并行数字信号的信号传输装置用于避免传输错误。 该装置包括用于接收在n位并行数字信号中连续发生的第一和第二n位数字数据的检测器，进行第一次计算以获得改变的值，并且在改变的值大于的情况下输出指示信号 阈值，电连接到用于接收指示信号的检测器和第二n位数字数据的编码器，进行第二次计算，并输出编码的第二n位数字数据，以减小第一n位数据之间的改变值 数字数据和低于阈值的编码的第二n位数字数据，以及电连接到检测器和编码器的解码器，其接收指示信号和编码的第二n位数字数据，进行第三计算，并且恢复第二n 位数字数据。

公开(公告)号：US06573902B1

公开(公告)日：2003-06-03

申请号：US09531035

申请日：2000-03-20

申请人： Ming-Hao Liao ,  Hung-Ta Pai

发明人： Ming-Hao Liao ,  Hung-Ta Pai

IPC分类号： G06T1140

CPC分类号： G06T11/40

摘要： The present invention discloses an apparatus and method for cache memory connection of texture mapping, applied in a computer graphic processing system by storing image texels in cache memories. The apparatus comprises a plurality of cache memories. An array of image texels are stored in a plurality of cache memories to reduce the area occupied by cache memories of the computer graphic processing system. Besides, the apparatus and method of the present invention can be applied in the well-known mapping methods: selecting the nearest point, bilinear filtering and trilinear filtering. A plurality of multiplexers are used to reorganize the plurality of cache memories so as to increase the utilization efficiency of the apparatus of the present invention.

摘要翻译： 本发明公开了一种通过将图像纹理存储在高速缓冲存储器中而应用于计算机图形处理系统中的用于纹理映射的高速缓存存储器连接的装置和方法。 该装置包括多个高速缓冲存储器。 图像纹迹的阵列存储在多个高速缓冲存储器中，以减少计算机图形处理系统的高速缓冲存储器占用的面积。 此外，本发明的装置和方法可以应用于众所周知的映射方法中：选择最近点，双线性滤波和三线性滤波。 多个多路复用器被用于重组多个高速缓冲存储器，从而提高本发明装置的利用效率。

公开(公告)号：US07119856B2

公开(公告)日：2006-10-10

申请号：US10146036

申请日：2002-05-16

申请人： Chien-Hsiu Huang ,  Hung-Ta Pai

发明人： Chien-Hsiu Huang ,  Hung-Ta Pai

IPC分类号： H04N5/44 ,  H04N5/455

CPC分类号： H04N5/455 ,  H04N21/4183 ,  H04N21/42607

摘要： A TV decoder. The decoder comprises a converter producing a plurality of first bits by sampling a base-band TV signal within a sampling period, and transmitting the first bits in groups, wherein the first bits in each one of the groups undergo parallel transmission through a plurality of first signals, and a demodulator receives the first bits and produces a plurality of second bits controlling the first signals, wherein the second bits are sequentially transmitted through a second signal input to the converter.

公开(公告)号：US06304482B1

公开(公告)日：2001-10-16

申请号：US09716247

申请日：2000-11-21

申请人： Hung-Ming Lin ,  Hung-Ta Pai

发明人： Hung-Ming Lin ,  Hung-Ta Pai

IPC分类号： G11C1140

CPC分类号： G11C11/417 ,  G11C7/22 ,  G11C7/24 ,  G11C11/419

摘要： An apparatus of reducing power consumption of a single-ended Static Random Access Memory (hereinafter referred as SRAM) is provided. The apparatus consists of at least an extra column of status memory cell and a majority detector by which a bit status of a written data is detected and by which the value of the bit status is written into the extra column of status memory cell. The apparatus further includes a data scrambler by which the written data is converted into a storage data with a minority of 0 bits based on the value of bit status and by which the storage data is written into the main single-ended SRAM cell. The apparatus further includes a data de-scrambler by which the storage data in the main single-ended SRAM cell is converted into its original format based on the value of bit status stored in the extra column of memory cell and by which the data in its original format is output. Since the data stored in the main single-ended SRAM cell has a majority of 1 bits, the apparatus can reduce the power consumption of the single-ended SRAM.

摘要翻译： 提供了降低单端静态随机存取存储器（以下称为SRAM）功耗的装置。 该装置至少包括一列状态存储器单元和多数检测器，通过该检测器检测写入数据的位状态，并将位状态的值写入状态存储单元的额外列。 该装置还包括数据加扰器，通过该数据加扰器，根据比特状态的值将写入的数据转换成具有少量0比特的存储数据，并将存储数据写入主单端SRAM单元。 该装置还包括数据解扰器，通过该数据解扰器，主单端SRAM单元中的存储数据基于存储在存储器单元的额外列中的位状态的值被转换成其原始格式， 输出原始格式。 由于存储在主单端SRAM单元中的数据大部分为1位，因此该器件可以降低单端SRAM的功耗。