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    Static random access memory cell and method of operating the same
    2.
    发明授权
    Static random access memory cell and method of operating the same 有权
    静态随机存取存储单元及其操作方法

    公开(公告)号：US08437178B2

    公开(公告)日：2013-05-07

    申请号：US13096796

    申请日：2011-04-28

    申请人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

    发明人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

    摘要翻译： 静态随机存取存储单元包括一个锁存单元。 锁存单元包括双向电路和开关电路。 双向电路具有第一端子和第二端子。 开关电路电连接在第一端子和第二端子之间，其中当开关电路导通时，开关电路在第一端子和第二端子之间形成用于锁存闩锁单元的反馈; 并且当切换电路关闭时，消除反馈以使SRAM单元向锁存单元写入数据位。

    GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE
    3.
    发明申请
    GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE 有权
    栅极氧化物断开电源开关结构

    公开(公告)号：US20120087196A1

    公开(公告)日：2012-04-12

    申请号：US13075682

    申请日：2011-03-30

    申请人： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

    发明人： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

    IPC分类号： G11C5/14

    CPC分类号： G11C11/417

    摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

    摘要翻译： 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

    DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
    4.
    发明申请
    DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL 有权
    无干扰的静态随机存取存储器单元

    公开(公告)号：US20110128796A1

    公开(公告)日：2011-06-02

    申请号：US12772238

    申请日：2010-05-03

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C11/412

    摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

    摘要翻译： 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

    Gate oxide breakdown-withstanding power switch structure
    5.
    发明授权
    Gate oxide breakdown-withstanding power switch structure 有权
    栅极氧化物击穿电源开关结构

    公开(公告)号：US08385149B2

    公开(公告)日：2013-02-26

    申请号：US13075682

    申请日：2011-03-30

    申请人： Hao-I Yang ,  Ching-Te Chuang ,  Wei Hwang

    发明人： Hao-I Yang ,  Ching-Te Chuang ,  Wei Hwang

    IPC分类号： G11C5/14

    CPC分类号： G11C11/417

    摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

    摘要翻译： 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

    Data-aware dynamic supply random access memory
    6.
    发明授权
    Data-aware dynamic supply random access memory 有权
    数据感知动态供应随机存取存储器

    公开(公告)号：US08345504B2

    公开(公告)日：2013-01-01

    申请号：US13009240

    申请日：2011-01-19

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

    IPC分类号： G11C11/40

    CPC分类号： G11C11/413 ,  G11C11/412

    摘要： A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

    摘要翻译： 提供具有多个单元的随机存取存储器（RAM）。 在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。 每个电池有两个逆变器; 电源控制器有两个电源开关。 对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

    STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME 有权
    静态随机访问存储单元及其操作方法

    公开(公告)号：US20120230086A1

    公开(公告)日：2012-09-13

    申请号：US13096796

    申请日：2011-04-28

    申请人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

    发明人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

    摘要翻译： 静态随机存取存储单元包括一个锁存单元。 锁存单元包括双向电路和开关电路。 双向电路具有第一端子和第二端子。 开关电路电连接在第一端子和第二端子之间，其中当开关电路导通时，开关电路在第一端子和第二端子之间形成用于锁存闩锁单元的反馈; 并且当切换电路关闭时，消除反馈以使SRAM单元向锁存单元写入数据位。

    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF
    9.
    发明申请
    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF 有权
    静态随机存取存储器和位线电压控制器

    公开(公告)号：US20140009999A1

    公开(公告)日：2014-01-09

    申请号：US13665941

    申请日：2012-11-01

    申请人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    发明人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413

    摘要： A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

    摘要翻译： 公开了一种静态随机存取存储器及其位线电压控制器。 位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。