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    Integrated chemical sensor for detecting odorous matters
    1.
    发明授权
    Integrated chemical sensor for detecting odorous matters 有权
    用于检测气味物质的集成化学传感器

    公开(公告)号：US08499613B2

    公开(公告)日：2013-08-06

    申请号：US13016086

    申请日：2011-01-28

    Applicant: Federico Giovanni Ziglioli ,  Amedeo Maierna ,  Flavio Francesco Villa ,  Ubaldo Mastromatteo ,  Gabriele Barlocchi

    Inventor： Federico Giovanni Ziglioli ,  Amedeo Maierna ,  Flavio Francesco Villa ,  Ubaldo Mastromatteo ,  Gabriele Barlocchi

    IPC: G01N7/04

    CPC classification number: G01N33/0009

    Abstract: A cartridge-like chemical sensor is formed by a housing having a base and a cover fixed to the base and provided with an input opening, an output hole and a channel for a gas to be analyzed. The channel extends in the cover between the input opening and the output hole and faces a printed circuit board carrying an integrated circuit having a sensitive region open toward the channel and of a material capable to bind with target chemicals in the gas to be analyzed. A fan is arranged in the housing, downstream of the integrated device, for sucking the gas after being analyzed, and is part of a thermal control system for the integrated circuit.

    Abstract translation: 盒式化学传感器由壳体形成，壳体具有固定到基座的基部和盖，并且设置有用于待分析气体的输入开口，输出孔和通道。 通道在输入开口和输出孔之间的盖中延伸，并且面向承载具有朝向通道开口的敏感区域的集成电路的印刷电路板和能够与要分析的气体中的目标化学物质结合的材料。 在集成装置的下游的壳体内设置风扇，用于在分析后吸入气体，并且是集成电路的热控制系统的一部分。

    CAPACITIVE SEMICONDUCTOR PRESSURE SENSOR
    2.
    发明申请
    CAPACITIVE SEMICONDUCTOR PRESSURE SENSOR 有权
    电容式半导体压力传感器

    公开(公告)号：US20120223402A1

    公开(公告)日：2012-09-06

    申请号：US13446976

    申请日：2012-04-13

    Applicant: Flavio Francesco Villa ,  Gabriele Barlocchi ,  Pietro Corona ,  Benedetto Vigna ,  Lorenzo Baldo

    Inventor： Flavio Francesco Villa ,  Gabriele Barlocchi ,  Pietro Corona ,  Benedetto Vigna ,  Lorenzo Baldo

    IPC: H01L29/84

    CPC classification number: G01L9/0073 ,  G01L9/0045

    Abstract: A capacitive semiconductor pressure sensor, comprising: a bulk region of semiconductor material; a buried cavity overlying a first part of the bulk region; and a membrane suspended above said buried cavity, wherein, said bulk region and said membrane are formed in a monolithic substrate, and in that said monolithic substrate carries structures for transducing the deflection of said membrane into electrical signals, wherein said bulk region and said membrane form electrodes of a capacitive sensing element, and said transducer structures comprise contact structures in electrical contact with said membrane and with said bulk region.

    Abstract translation: 一种电容半导体压力传感器，包括：半导体材料的主体区域; 覆盖大块区域的第一部分的掩埋腔; 以及悬浮在所述掩埋腔上方的膜，其中所述体积区域和所述膜形成在整体式衬底中，并且所述整体式衬底承载用于将所述膜的偏转转换成电信号的结构，其中所述体积区域和所述膜 形成电容感测元件的电极，并且所述换能器结构包括与所述膜电连接并与所述体积区域接触的接触结构。

    PROCESS FOR MANUFACTURING A SEMICONDUCTOR WAFER HAVING SOI-INSULATED WELLS AND SEMICONDUCTOR WAFER THEREBY MANUFACTURED
    3.
    发明申请
    PROCESS FOR MANUFACTURING A SEMICONDUCTOR WAFER HAVING SOI-INSULATED WELLS AND SEMICONDUCTOR WAFER THEREBY MANUFACTURED 有权
    制造具有SOI绝缘管的半导体波导的制造方法和制造的半导体波形

    公开(公告)号：US20110133186A1

    公开(公告)日：2011-06-09

    申请号：US13023039

    申请日：2011-02-08

    Applicant: Gabriele BARLOCCHI ,  Pietro CORONA ,  Flavio Francesco VILLA

    Inventor： Gabriele BARLOCCHI ,  Pietro CORONA ,  Flavio Francesco VILLA

    IPC: H01L29/08 ,  H01L23/58

    CPC classification number: H01L21/76264 ,  H01L21/7682

    Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

    Abstract translation: 制造包括SOI绝缘阱的半导体晶片的工艺包括在半导体主体的管芯区域中形成穿过掩埋腔并分布在管芯区域中的掩埋腔和半导体结构元件。 该方法还包括选择性地将第一相邻的半导体结构元件氧化并设置在封闭区域内的步骤，并且防止第二半导体结构元件在封闭区域外的氧化，从而在闭合区域内选择性地形成管芯埋入介质层。

    Process for manufacturing wafers usable in the semiconductor industry
    4.
    发明授权
    Process for manufacturing wafers usable in the semiconductor industry 有权
    用于制造可用于半导体工业的晶圆的工艺

    公开(公告)号：US07524736B2

    公开(公告)日：2009-04-28

    申请号：US11607802

    申请日：2006-12-01

    Applicant: Giampiero Ottaviani ,  Federico Corni ,  Paolo Ferrari ,  Flavio Francesco Villa

    Inventor： Giampiero Ottaviani ,  Federico Corni ,  Paolo Ferrari ,  Flavio Francesco Villa

    IPC: H01L21/30 ,  C03C15/00

    CPC classification number: H01L21/76254

    Abstract: To manufacture a layer of semiconductor material, a first wafer of semiconductor material is subjected to implantation to form a defect layer at a distance from a first face; the first wafer is bonded to a second wafer, by putting an insulating layer present on the second wafer in contact with the first face of the first wafer. Then, hydrogen atoms are introduced into the first wafer through a second face at an energy such as to avoid defects to be generated in the first wafer and at a temperature lower than 600° C. Thereby, the first wafer splits into a usable layer, bonded to the second wafer, and a remaining layer disposed between the defect layer and the second face of the first wafer. Prior to bonding, the first wafer is subjected to processing steps for obtaining integrated components.

    Abstract translation: 为了制造半导体材料层，将半导体材料的第一晶片进行注入以形成距离第一面一定距离的缺陷层; 通过将存在于第二晶片上的绝缘层与第一晶片的第一面接触来将第一晶片接合到第二晶片。 然后，氢原子通过第二面以能量引入第一晶片，以避免在第一晶片中以及在低于600℃的温度下产生缺陷。由此，第一晶片分裂成可用层， 粘合到第二晶片，以及设置在第一晶片的缺陷层和第二面之间的剩余层。 在接合之前，第一晶片经受用于获得集成部件的处理步骤。

    Process for manufacturing wafers of semiconductor material by layer transfer
    6.
    发明授权
    Process for manufacturing wafers of semiconductor material by layer transfer 有权
    通过层转移制造半导体材料的晶片的工艺

    公开(公告)号：US07348257B2

    公开(公告)日：2008-03-25

    申请号：US11225883

    申请日：2005-09-13

    Applicant: Gabriele Barlocchi ,  Flavio Francesco Villa

    Inventor： Gabriele Barlocchi ,  Flavio Francesco Villa

    IPC: H01L21/30

    CPC classification number: H01L21/3247 ,  H01L21/3043 ,  H01L21/76251 ,  H01L21/76259

    Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.

    Abstract translation: 一种工艺使用半导体处理技术制造晶片。 在第一晶片的顶表面上形成接合层; 在属于第二晶片的半导体材料的衬底中挖出深沟槽。 半导体材料的顶层形成在衬底的顶部上，以封闭顶部的深沟槽并形成至少一个埋入空腔。 第二晶片的顶层通过结合层结合到第一晶片。 对这两个晶片进行热处理，其导致顶层的至少一部分与第一晶片的接合和掩埋腔的加宽。 以这种方式，将结合到第一晶片的顶层的部分与第二晶片的其余部分分离，以形成复合晶片。

    Process for manufacturing thick suspended structures of semiconductor material
    9.
    发明授权
    Process for manufacturing thick suspended structures of semiconductor material 有权
    用于制造半导体材料的厚悬浮结构的方法

    公开(公告)号：US07871894B2

    公开(公告)日：2011-01-18

    申请号：US11541376

    申请日：2006-09-27

    Applicant: Pietro Corona ,  Flavio Francesco Villa ,  Gabriele Barlocchi

    Inventor： Pietro Corona ,  Flavio Francesco Villa ,  Gabriele Barlocchi

    IPC: H01L21/76

    CPC classification number: B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

    Abstract: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.

    Abstract translation: 制造半导体材料的悬浮结构的方法设想的步骤：提供具有正面的半导体材料的整体; 在所述整体式主体内形成掩埋空腔，所述掩埋腔在所述前表面的一定距离处延伸并且与所述前表面一起界定所述整体式主体的表面区域，所述表面区域具有第一厚度; 进行增稠热处理，使得整体式体的半导体材料朝向表面区域移动，从而在掩埋空腔之上形成悬浮结构，该悬浮结构的第二厚度大于第一厚度。 增稠热处理是退火处理。

    Integrated differential pressure sensor and manufacturing process thereof
    10.
    发明授权
    Integrated differential pressure sensor and manufacturing process thereof 有权
    集成差压传感器及其制造工艺

    公开(公告)号：US07763487B2

    公开(公告)日：2010-07-27

    申请号：US11417683

    申请日：2006-05-04

    Applicant: Flavio Francesco Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    Inventor： Flavio Francesco Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    IPC: H01L21/00 ,  H01L29/84

    CPC classification number: G01L9/0045 ,  G01L13/025

    Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

    Abstract translation: 一种用于制造集成差压传感器的方法，包括在具有第一面和第二面的半导体材料的整体中形成一个与第一面相距一定距离的空腔，并将其限定在柔性膜上，形成入口通道 与空腔流体连通，以及在柔性膜中形成至少一个换能元件，其构造成将柔性膜的变形转换为电信号。 空腔形成在距第二面一定距离处的位置，并与第二面一起界定整体式的一部分。 为了形成进入通道，对整体式主体进行蚀刻以便形成延伸通过其的通道沟槽。

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