公开(公告)号：US06401194B1

公开(公告)日：2002-06-04

申请号：US08790142

申请日：1997-01-28

申请人： Le Trong Nguyen ,  Heonchul Park ,  Roney S. Wong ,  Ted Nguyen ,  Edward H. Yu

发明人： Le Trong Nguyen ,  Heonchul Park ,  Roney S. Wong ,  Ted Nguyen ,  Edward H. Yu

IPC分类号： G06F9302

CPC分类号： G06F7/57 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F2207/382 ,  G06F2207/3828

摘要： A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

摘要翻译： 向量处理器提供分割成更小的数据片段的数据路径，每个片段与其他片段并行处理。 此外，执行单元提供较小的算术和功能单元链接在一起，以通过共享单周期操作来执行需要多个周期的更复杂的微处理器指令，从而降低了微处理器的成本和尺寸。 一个实施例使用36位数据路径片处理288位数据宽度。 另一个实施例使用单周期算术逻辑单元执行整数乘法和乘法和累加和浮点加法和减法运算。 其他实施例支持8位，9位，16位和32位整数数据类型和32位浮点数据类型。

公开(公告)号：US5877636A

公开(公告)日：1999-03-02

申请号：US733885

申请日：1996-10-18

申请人： Ho D. Truong ,  Edward H. Yu ,  Kathy Ying Chen

发明人： Ho D. Truong ,  Edward H. Yu ,  Kathy Ying Chen

IPC分类号： H03K17/62 ,  H03K5/135 ,  H03K5/13 ,  H03K17/00

CPC分类号： H03K5/135

摘要： An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state. The apparatus further includes a second means for coupling a second test clock signal to a second output clock when the test mode control signal is active, for driving the second output clock to the inactive clock signal level when the test mode control signal transitions to the inactive state, and for coupling a second system clock signal to the second output clock beginning with a first full clock pulse of the second system clock signal which occurs after the first full clock pulse of the first system clock signal. When exiting the test mode the apparatus ensures that both first and second output clock signals are brought (or held) to an inactive clock signal level, and that system operation begins with the first system clock signal.

摘要翻译： 一种用于将一对测试时钟信号和一对系统时钟信号复用到一对输出时钟信号上的装置包括：当测试模式控制信号有效时将第一测试时钟信号耦合到第一输出时钟信号的第一装置， 用于当所述测试模式控制信号转变到非活动状态时将所述第一输出时钟信号驱动到非活动时钟信号电平，并且用于将所述第一系统时钟信号与所述第一系统的第一全时钟脉冲开始的所述第一输出时钟信号耦合 在测试模式控制信号转变到无效状态之后发生的时钟信号。 该装置还包括第二装置，用于当测试模式控制信号有效时将第二测试时钟信号耦合到第二输出时钟，用于当测试模式控制信号转换到非活动状态时将第二输出时钟驱动到非活动时钟信号电平 状态，并且用于将第二系统时钟信号耦合到第二输出时钟，从第一系统时钟信号的第一全时钟脉冲之后出现的第二系统时钟信号的第一全时钟脉冲开始。 当退出测试模式时，装置确保第一和第二输出时钟信号都被带入（或保持）到不活动时钟信号电平，并且系统操作以第一系统时钟信号开始。

公开(公告)号：US5822231A

公开(公告)日：1998-10-13

申请号：US741991

申请日：1996-10-31

申请人： Roney S. Wong ,  Edward H. Yu

发明人： Roney S. Wong ,  Edward H. Yu

IPC分类号： G06F5/01 ,  G06F7/00

CPC分类号： G06F5/015

摘要： A modular two level nine bit shift apparatus has a second level shifter which receives nine input data bits and second level shift signals. The second level shifter shifts the nine data bits by 0, 3 or 6 bit positions according to the second level shift signals and outputs nine second level data bits. A first level shifter receives the nine second level data bits and first level shift signals. The first level shifter shifts the nine second level data bits by 0, 1 or 2, bit positions according to the first level shift signals. The first and second level shifter combine to provide a shift of from 0 to 8 bits. The nine bit shifter can also accommodate eight bit data. The 9 bit shift count is decoded by dividing the count into a first block (0, 1, 2), a second block (3, 4, 5) and a third block (6, 7, 8). Block select signals select one of the first, second and third blocks and the bit select signals select one of the three shift counts within each block. A decode of the block select signals are coupled to the second level shifter as the second level shift signal and a decode of the bit select signals are coupled to the first level shifter as the first level shift signal. Therefore, the block select signals specify shifts of 0, 3, or 6 bits and the bit select signals specify shifts of 0, 1 or 2 bits, to specify a total shift of between 0 and 8 bits. The nine bit two level modular shifter can be used to create a wider shift comprised of three levels. The third level shifter which includes 4 9-bit 4:1 multiplexers, receives thirty six input bits and third level shift signals. The third level shifter outputs the thirty six input bits shifted by 0, 9, 18, or 27, which are then supplied to four two level 9 bit shifters to provide a full 36 bit shift/rotate operation.

摘要翻译： 模块化二级9位移位装置具有第二电平移位器，其接收九个输入数据位和第二电平移位信号。 第二电平移位器根据第二电平移位信号将九个数据位移位0,3或6位位置，并输出九个第二电平数据位。 第一电平移位器接收九个第二电平数据位和第一电平移位信号。 第一电平移位器根据第一电平移位信号将九个第二电平数据位移位0,1或2位位置。 第一和第二电平移位器组合以提供从0到8位的移位。 九位移位器也可以容纳8位数据。 通过将计数分成第一块（0,1,2），第二块（3,4,5）和第三块（6,7,8））来解码9位移位计数。 块选择信号选择第一，第二和第三块中的一个，并且位选择信号选择每个块内的三个移位计数之一。 块选择信号的解码作为第二电平移位信号耦合到第二电平移位器，并且位选择信号的解码被耦合到第一电平移位器作为第一电平移位信号。 因此，块选择信号指定0,3或6位的移位，并且位选择信号指定0,1或2位的移位，以指定0和8位之间的总移位。 九位二级模块化移位器可用于创建由三个级别组成的更宽的移位。 包括4个9位4：1复用器的第三电平移位器接收三十六个输入位和第三电平移位信号。 第三电平移位器输出移位了0,9,18或27的三十六个输入位，然后将其提供给四个两个9位移位器，以提供完整的36位移位/旋转运算。