Error correction system in a processing agent having minimal delay
    2.
    发明授权
    Error correction system in a processing agent having minimal delay 有权
    具有最小延迟的处理代理中的纠错系统

    公开(公告)号:US06269465B1

    公开(公告)日:2001-07-31

    申请号:US09197582

    申请日:1998-11-23

    IPC分类号: H03M1300

    CPC分类号: H03M13/03

    摘要: An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.

    摘要翻译: 代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。 当检测到在代理内部要处理的数据的数据错误时,纠错系统将损坏的数据通过纠错电路,并从代理程序中传回代理。 当检测到数据错误时,错误修正将内部数据请求更改为外部事务。

    Transaction manager and cache for processing agent
    6.
    发明授权
    Transaction manager and cache for processing agent 失效
    处理代理的事务管理器和缓存

    公开(公告)号:US08122194B2

    公开(公告)日:2012-02-21

    申请号:US12468360

    申请日:2009-05-19

    IPC分类号: G06F12/00 G06F13/00

    CPC分类号: G06F12/0893 G06F12/0886

    摘要: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.

    摘要翻译: 处理代理被用于在外部事务期间传送预定数据线长度的数据的系统。 代理可以包括具有多个高速缓存条目的内部高速缓存。 每个缓存条目可以存储多条数据线长度的数据。 代理还可以包括具有队列条目的事务队列系统,该队列条目包括包括地址部分和状态部分的主条目,为代理的第一外部事务提供的状态部分,以及包括为第二条提供的状态部分的辅助条目 外部交易。

    Method and apparatus for altering data length to zero to maintain cache coherency
    7.
    发明授权
    Method and apparatus for altering data length to zero to maintain cache coherency 失效
    将数据长度改变为零以维持高速缓存一致性的方法和装置

    公开(公告)号:US06735675B2

    公开(公告)日:2004-05-11

    申请号:US10346060

    申请日:2003-01-17

    IPC分类号: G06F1200

    CPC分类号: G06F12/0831

    摘要: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

    摘要翻译: 通过允许所有显式回写在窥探阶段继续进行,从而提高了多代理系统的效率。 在每个传入的外部总线请求时,代理确定该请求的地址是否匹配代理中的数据的地址。 如果有匹配,代理将复制最近的数据,将数据的状态更改为未修改,将数据的长度更改为零(用于挂起的显式回写),并执行隐式的回写。 另外,在每个显式回写之前,代理确定显式回写的地址和任何进入的窥探请求请求是否相同。 如果存在匹配,代理将在显式回写之前将显式回写的数据长度更改为零。

    Prioritized bus request scheduling mechanism for processing devices
    10.
    发明授权
    Prioritized bus request scheduling mechanism for processing devices 有权
    用于处理设备的优先总线请求调度机制

    公开(公告)号:US06499090B1

    公开(公告)日:2002-12-24

    申请号:US09474010

    申请日:1999-12-28

    IPC分类号: G06F1300

    摘要: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.

    摘要翻译: 调度器存储要调度的数据。 调度器可以包括根据第一优先级方案(例如按年龄)标识队列条目中的相对优先级的阵列。 调度器还可以包括优先级寄存器阵列,其根据第二优先级方案,例如通过数据类型来标识队列条目中的相对优先级。 耦合到阵列和优先级寄存器阵列的多个检测器可以确定下一个要调度的数据。