公开(公告)号：US08001438B1

公开(公告)日：2011-08-16

申请号：US12192741

申请日：2008-08-15

申请人： Deepak M. Pabari

发明人： Deepak M. Pabari

IPC分类号： G01R31/28 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G01R31/08 ,  G01R31/02 ,  G06F11/00 ,  G06F17/50 ,  G06F9/455 ,  G06F11/22 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/10 ,  G01R31/31835

摘要： A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern (610, 620). Pairs of nets in the circuit design that are adjacent can be identified (625). Each type of bridge fault for which each pair is tested can be determined according to the simulation results (640, 645, 655, 660). A measure of bridge fault coverage for the test pattern can be calculated according to which types of bridge faults each pair is tested and which net of each pair acts as an aggressor for each type of bridge fault tested (675). The measure of bridge fault coverage can be output (680).

摘要翻译： 用于测量在可编程逻辑器件内实现的电路设计的测试图案的桥接器故障覆盖的计算机实现方法可以包括识别模拟结果并且停留在测试图案（610,620）的电路设计的覆盖范围。 可以识别相邻电路设计中的网对（625）。 可以根据模拟结果（640,655,655,660）确定每对测试的每种类型的桥式故障。 可以根据每对测试的桥型故障类型来计算测试模式的桥梁故障覆盖度，并且每对桥梁的每个网络作为每种类型的桥接故障测试（675）的侵略者。 可以输出桥接故障覆盖度量（680）。

公开(公告)号：US07430697B1

公开(公告)日：2008-09-30

申请号：US11186373

申请日：2005-07-21

申请人： Deepak M. Pabari

发明人： Deepak M. Pabari

IPC分类号： G01R31/28

CPC分类号： G01R31/318516 ,  G01R31/31717

摘要： A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit; routing the test signal source to the logic circuit; and determining if the logic circuit is defective. According to an alternate embodiment, a method enables re-routing a path from a shift register to a lookup table to determine whether a lookup table is defective. According to a further alternate embodiment, a method enables localized routing to reduce the probability that a defect is a result of a routing defect.

摘要翻译： 描述了在可编程逻辑器件中测试电路的方法。 根据本发明的一个实施例，一种方法包括用测试信号源和逻辑电路配置可编程逻辑器件的可配置逻辑块的步骤; 将测试信号源路由到逻辑电路; 并确定逻辑电路是否有缺陷。 根据替代实施例，一种方法使得能够将路由从移位寄存器重新路由到查找表以确定查找表是否有缺陷。 根据另一替代实施例，一种方法使得能够进行局部路由以减少缺陷是路由缺陷的结果的可能性。