公开(公告)号：US20080175270A1

公开(公告)日：2008-07-24

申请号：US11625884

申请日：2007-01-23

Applicant: Deepak Kataria ,  Chengzhou Li

Inventor： Deepak Kataria ,  Chengzhou Li

IPC: H04J3/22

CPC classification number: H04J3/24

Abstract: A multi-stage scheduler that provides improved bandwidth utilization in the presence of processor intensive traffic is disclosed. Incoming traffic is separated into multiple traffic flows. Data blocks of the traffic flows are scheduled for access to a processor resource using a first scheduling algorithm, and processed by the processor resource as scheduled by the first scheduling algorithm. The processed data blocks of the traffic flows are scheduled for access to a bandwidth resource using a second scheduling algorithm, and provided to the bandwidth resource as scheduled by the second scheduling algorithm. The multi-stage scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of a communication system.

Abstract translation: 公开了一种在存在处理器密集型业务的情况下提供改进的带宽利用率的多级调度器。 入站流量分为多个流量。 业务流的数据块被调度为使用第一调度算法对处理器资源进行访问，并由处理器资源按照第一调度算法调度进行处理。 业务流的处理数据块被调度为使用第二调度算法对带宽资源进行访问，并且被提供给由第二调度算法调度的带宽资源。 说明性实施例中的多级调度器可以在通信系统的网络处理器集成电路或其他处理设备中实现。

公开(公告)号：US06385172B1

公开(公告)日：2002-05-07

申请号：US09272720

申请日：1999-03-19

Applicant: Deepak Kataria ,  Dimitris Logothetis ,  Santhanam Srinivasan ,  Malathi Veeraraghavan

Inventor： Deepak Kataria ,  Dimitris Logothetis ,  Santhanam Srinivasan ,  Malathi Veeraraghavan

IPC: H04J116

CPC classification number: H04L45/00 ,  H04L45/124 ,  H04Q3/0016 ,  H04Q2213/13003 ,  H04Q2213/1305 ,  H04Q2213/1307 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/1313 ,  H04Q2213/13164 ,  H04Q2213/13166 ,  H04Q2213/13176 ,  H04Q2213/13178 ,  H04Q2213/13299 ,  H04Q2213/13335 ,  H04Q2213/13349 ,  H04Q2213/1338

Abstract: Methods and communication networks having a plurality of connection-oriented switches in which administrative weights are assigned based on link call blocking probabilities. Three assignment schemes include, first, a solution that can be built in the switch software of sufficiently similar switches to enable the switches to determine administrative weights for their links. The second and third schemes employ administrative weight management stations. The second scheme uses an administrative weight management station that operates to enhance total network revenue or throughput in a communication network in which all of the switches implement a certain type of accounting management information databases (MIB). The third scheme uses an administrative weight management station that computes administrative weights for switches that do not have the capability for the second scheme, but which employ appropriate MIBs.

Abstract translation: 具有多个面向连接的交换机的方法和通信网络，其中基于链路呼叫阻塞概率来分配管理权重。 三种分配方案首先包括可以在交换机软件中构建足够相似的交换机的解决方案，以使交换机能够确定其链路的管理权重。 第二和第三种方案采用行政权重管理站。 第二种方案使用管理权重管理站，其操作以增强其中所有交换机实现某种类型的会计管理信息数据库（MIB）的通信网络中的总网络收入或吞吐量。 第三种方案使用管理权重管理站，其计算对于不具有第二方案的能力但是使用适当的MIB的交换机的管理权重。

公开(公告)号：US20080080563A1

公开(公告)日：2008-04-03

申请号：US11536848

申请日：2006-09-29

Applicant: Deepak Kataria ,  Chengzhou Li

Inventor： Deepak Kataria ,  Chengzhou Li

IPC: H04J3/06

CPC classification number: H04J3/0664 ,  H03L7/08 ,  H03L2207/50

Abstract: Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of a receive node in a packet network are provided. Receive time stamps are generated for transferred packets at a receive node in-accordance with the second clock. Propagation delay variation is filtered from receive time stamp intervals through a filter in accordance with a frequency of the second clock. The filtered receive time stamp intervals and transmit time stamp intervals of the transferred packets are input into a phase locked loop to generate a new frequency for the second clock. The filter and the second clock are updated in accordance with the new frequency for synchronization with the first clock of the transfer node.

Abstract translation: 提供了用于在分组网络中同步发送节点的第一时钟和接收节点的第二时钟的方法和装置。 根据第二个时钟在接收节点处为传输的分组生成接收时间戳。 根据第二时钟的频率，通过滤波器从接收时间戳间隔过滤传播延迟变化​​。 经过滤波的接收时间戳间隔和传送的分组的传输时间戳间隔被输入到锁相环以产生第二时钟的新频率。 根据用于与传送节点的第一时钟同步的新频率来更新滤波器和第二时钟。

公开(公告)号：US07177279B2

公开(公告)日：2007-02-13

申请号：US10131577

申请日：2002-04-24

Applicant: Deepak Kataria

Inventor： Deepak Kataria

IPC: H04J3/14

CPC classification number: H04L12/5601 ,  H04L2012/5648 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5682

Abstract: In one embodiment, an apparatus for coordinating merging of packets for one or more virtual circuits (VGs). Each packet of a VC comprising a sequence of cells terminates with an end of packet (EOP) cell. The apparatus comprises one or more buffers, a buffer controller, and a merge processor. Each buffer is configured to receive cells of an associated VC and a threshold value based on traffic of the VC. When a number of cells of a packet in a buffer exceeds the corresponding dynamic threshold value, a corresponding flag of the buffer is set. The buffer controller is configured to drop all cells of the current packet in response to a set flag of a corresponding buffer. The merge processor services each buffer in accordance with a scheduling method to transfer one or more packets from each buffer to an output packet stream.

Abstract translation: 在一个实施例中，一种用于协调用于一个或多个虚拟电路（VG）的分组的合并的装置。 包含单元序列的VC的每个包终止于包（EOP）单元的结尾。 该装置包括一个或多个缓冲器，缓冲器控制器和合并处理器。 每个缓冲器被配置为基于VC的流量接收相关联的VC的小区和阈值。 当缓冲器中的分组的小区的数量超过相应的动态阈值时，设置缓冲器的相应标志。 缓冲器控制器被配置为响应于相应缓冲器的设置标志来丢弃当前分组的所有单元。 合并处理器根据调度方法为每个缓冲器服务以将一个或多个分组从每个缓冲器传送到输出分组流。

公开(公告)号：US07924857B2

公开(公告)日：2011-04-12

申请号：US11326047

申请日：2006-01-05

Applicant: Deepak Kataria ,  Codrut Radu Radulescu

Inventor： Deepak Kataria ,  Codrut Radu Radulescu

IPC: H04L12/56

CPC classification number: H04L49/9094 ,  H04L49/90

Abstract: A method and apparatus of reorganizing cells received over data communication lines at a receive node is provided. The cells have an initial order identified by monotonically increasing sequence identifiers. The receive node has buffers associated with respective ones of the communication lines. Each of the buffers has an output position. A cell having a smallest sequence identifier is detected from one or more cells at the output positions of the buffers. It is determined if the smallest sequence identifier is sequentially consecutive to a specified sequence identifier. If the smallest sequence identifier is sequentially consecutive to the specified sequence identifier, the cell having the smallest sequence identifier is dequeued from an output position of one of the buffers and the specified sequence identifier is redefined as the smallest sequence identifier.

Abstract translation: 提供了一种在接收节点上通过数据通信线路重新组合接收的小区的方法和装置。 单元具有通过单调增加序列标识符来识别的初始顺序。 接收节点具有与相应通信线路相关联的缓冲器。 每个缓冲器都有一个输出位置。 从缓冲器的输出位置的一个或多个单元检测具有最小序列标识符的单元。 确定最小序列标识符是否与指定的序列标识符顺序连续。 如果最小的序列标识符与指定的序列标识符顺序连续，则具有最小序列标识符的小区从一个缓冲区的输出位置出出，并且将指定的序列标识符重新定义为最小的序列标识符。

公开(公告)号：US20080037441A1

公开(公告)日：2008-02-14

申请号：US11459035

申请日：2006-07-21

Applicant: Deepak Kataria ,  Seong-Hwan Kim ,  Sundar Vedantham

Inventor： Deepak Kataria ,  Seong-Hwan Kim ,  Sundar Vedantham

IPC: H04L12/28

CPC classification number: H04L12/2856 ,  H04L12/2896 ,  H04L63/1458

Abstract: Methods and apparatus for use with an integrated circuit device of a processing device of a network node of a digital networking system, configured to monitor one or more control messages received at the processing device from each of a plurality of CPE devices, and limiting the one or more control messages to one or more specified rates for a specified duration. The integrated circuit device is further configured to provide one or more data channels to the plurality of CPE devices from the processing device in response to the one or more control messages processed at the processing device.

Abstract translation: 与数字网络系统的网络节点的处理设备的集成电路设备一起使用的方法和装置，被配置为监视从多个CPE设备中的每一个处理设备接收的一个或多个控制消息，并且限制一个 或更多的控制消息到一个或多个指定的速率在指定的持续时间。 集成电路设备还被配置为响应于处理设备处理的一个或多个控制消息，从处理设备向多个CPE设备提供一个或多个数据信道。

公开(公告)号：US20070025356A1

公开(公告)日：2007-02-01

申请号：US11193799

申请日：2005-07-29

Applicant: Deepak Kataria ,  Codrut Radulescu

Inventor： Deepak Kataria ,  Codrut Radulescu

IPC: H04L12/56

CPC classification number: H04L47/30 ,  H04L45/245 ,  H04L47/34 ,  H04L49/90

Abstract: A method of minimizing SID difference of simultaneously transmitted cells in two or more data communication lines is provided. A data transmission speed of each of the two or more data communication lines is identified. A fullness threshold of at least one buffer of two or more buffers in a transmit node is configured in relation to a size of a data cell for transmission. The two or more buffers correspond to respective ones of the two or more data communication lines. The at least one buffer communicates with a given one of the two or more data communication lines having a data transmission speed slower than another of the two or more data communication lines. One or more data cells for transmission are assigned to the two or more buffers of the two or more data communication lines at the transmit node. The one or more data cells are transmitted from the transmit node to a receive node in accordance with the data transmission speeds of the two or more data communication lines. The fullness threshold of the at least one buffer controls assignment of data cells to the at least one buffer during data cell transmission on the given data communication line and minimizes SID difference of simultaneously transmitted cells in the two or more data communication lines.

Abstract translation: 提供了一种使两个或多个数据通信线路中的同时发送的小区的SID差异最小化的方法。 识别两条或多条数据通信线路中的每一条的数据传输速度。 发送节点中的两个或更多个缓冲器的至少一个缓冲器的饱和度阈值被配置为用于传输的数据单元的大小。 两个或更多个缓冲器对应于两个或更多个数据通信线路中的相应的缓冲器。 所述至少一个缓冲器与所述两条或更多条数据通信线路中的给定的一条数据传输速度比所述两条或更多条数据通信线路中的另一条数据传输速度慢。 用于发送的一个或多个数据单元被分配给发送节点处的两个或更多个数据通信线路的两个或更多个缓冲器。 根据两条或多条数据通信线路的数据传输速度，一个或多个数据信元从发送节点发送到接收节点。 所述至少一个缓冲器的饱和度阈值在所述给定数据通信线路上的数据单元传输期间控制数据单元向所述至少一个缓冲器的分配，并且最小化两个或更多个数据通信线路中同时发送的小区的SID差异。

公开(公告)号：US20060013210A1

公开(公告)日：2006-01-19

申请号：US10871440

申请日：2004-06-18

Applicant: Mark Bordogna ,  Christopher Hamilton ,  Deepak Kataria ,  Pravin Pathak ,  Mark Simkins

Inventor： Mark Bordogna ,  Christopher Hamilton ,  Deepak Kataria ,  Pravin Pathak ,  Mark Simkins

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L45/00 ,  H04L45/24 ,  H04L47/122 ,  H04L47/2416 ,  H04L47/2441

Abstract: A method and apparatus are disclosed for per-service flow protection and restoration of data in one or more packet networks. The disclosed protection and restoration techniques allow traffic to be prioritized and protected from the aggregate level down to a micro-flow level. Thus, protection can be limited to those services that are fault sensitive. Protected data is duplicated over a primary path and one or more backup data paths. Following a link failure, protected data can be quickly and efficiently restored without significant service interruption. A received packet is classified at each end point based on information in a header portion of the packet, using one or more rules that determine whether the received packet should be protected. At an ingress node, if the packet classification determines that the received packet should be protected, then the received packet is transmitted on at least two paths. At an egress node, if the packet classification determines that the received packet is protected, then multiple versions of the received packet are expected and only one version of the received packet is transmitted.

Abstract translation: 公开了用于一个或多个分组网络中的每个服务流保护和数据恢复的方法和装置。 所公开的保护和恢复技术允许流量被优先排序并从聚合级别保护到微流量级别。 因此，保护​​可以限于那些故障敏感的服务。 受保护的数据在主路径和一个或多个备份数据路径上复制。 在链路故障之后，可以快速有效地恢复受保护的数据，而不会有重大的业务中断。 使用确定接收到的分组是否应被保护的一个或多个规则，基于分组的报头部分中的信息，在每个终点处分类所接收的分组。 在入口节点，如果分组分类确定接收到的分组应该被保护，则所接收的分组在至少两个路径上被传送。 在出口节点，如果分组分类确定接收到的分组被保护，则预期接收分组的多个版本，并且仅传送所接收分组的一个版本。

公开(公告)号：US06661797B1

公开(公告)日：2003-12-09

申请号：US09514725

申请日：2000-02-28

Applicant: Ashish Goel ,  Deepak Kataria ,  Dimitris Logothetis ,  Kajamalai Gopalaswamy Ramakrishnan

Inventor： Ashish Goel ,  Deepak Kataria ,  Dimitris Logothetis ,  Kajamalai Gopalaswamy Ramakrishnan

IPC: H04L1228

CPC classification number: H04L45/00 ,  H04L45/121

Abstract: Arrangements and methods for efficiently selecting an optimum connection path that meets user specified delay requirements with enhanced efficiency. In a basic aspect, a method is implemented by one of a plurality of algorithms to meet user QoS specifications. The user not only specifies a delay threshold T for the incoming request but also specifies a delay threshold tolerance &egr; for the path delay that will satisfy him. Two implementations are disclosed. The first is termed non-iterative and sets scaling factor &tgr;=min (T, (n−1)/&egr;), where n is a number of links in a shortest path, scales all the relevant delay parameters by &tgr;/T, truncates all the scaled values to integers, and uses a dynamic programming algorithm to accumulate the total of resulting link delay parameters values for each possible shortest path. The second method, termed iterative, is similar, except that it sets &tgr;

Abstract translation: 有效选择满足用户指定的延迟要求并提高效率的最佳连接路径的安排和方法。 在一个基本方面，一种方法由多种算法中的一种来实现，以满足用户QoS规范。 用户不仅为传入请求指定了延迟阈值T，还指定了将满足他的路径延迟的延迟阈值容差ε。 公开了两种实现方式。 第一个称为非迭代，并设置缩放因子τt = min（T，（n-1）/ epsilon），其中n是最短路径中的链路数，将所有相关延迟参数缩放为tau / T，截断 将所有缩放的值作为整数，并使用动态编程算法来累积每个可能的最短路径的结果链路延迟参数值的总和。 称为迭代的第二种方法是类似的，只是它设置tau << T。 然后，如果缩放，截断和累加步骤不能满足客户规格，则下一次迭代将两倍。 两种方法都以计算有效的方式计算从一个源到所有目的地的路径。

公开(公告)号：US20140105592A1

公开(公告)日：2014-04-17

申请号：US13652156

申请日：2012-10-15

Applicant: Deepak Kataria ,  Jian-lin Mu ,  Michael Green ,  John Brian Pipe

Inventor： Deepak Kataria ,  Jian-lin Mu ,  Michael Green ,  John Brian Pipe

IPC: H04B10/08

CPC classification number: H04B10/032

Abstract: The present disclosure includes a network element comprising a first card configured to receive a duplicatively split first signal comprising a data component and a management component, and further configured to receive and transmit a duplicatively split second signal, and a similar second card. The network element also includes a selector configured to select either the first card or the second card to receive the management component of the first signal and to detect a change in designation between the first card and the second card to transmit the second signal. The selector is also configured to modify the selection to select the card designated to transmit the second signal to also receive the management component of the first signal. The disclosure also includes associated methods and systems.

Abstract translation: 本公开包括网络元件，其包括被配置为接收包括数据组件和管理组件的重复分割的第一信号的第一卡，并且还被配置为接收和发送重复分割的第二信号和类似的第二卡。 网络元件还包括选择器，其被配置为选择第一卡或第二卡以接收第一信号的管理组件，并且检测第一卡和第二卡之间的指定变化以发送第二信号。 选择器还被配置为修改选择以选择指定为发送第二信号的卡，以接收第一信号的管理组件。 本公开还包括相关联的方法和系统。