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1.发明授权Processing system with interspersed processors using shared memory of communication elements 有权具有散布处理器的处理系统使用通信元件的共享存储器公开(公告)号：US07987338B2
公开(公告)日：2011-07-26
申请号：US12781314
申请日：2010-05-17
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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2.发明申请公开(公告)号：US20100268914A1
公开(公告)日：2010-10-21
申请号：US12827416
申请日：2010-06-30
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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3.发明授权Processing system with interspersed stall propagating processors and communication elements 有权具有散布的失速传播处理器和通信元件的处理系统公开(公告)号：US07415594B2
公开(公告)日：2008-08-19
申请号：US10602292
申请日：2003-06-24
IPC分类号： G06F15/00
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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4.发明申请公开(公告)号：US20080148009A1
公开(公告)日：2008-06-19
申请号：US12028565
申请日：2008-02-08
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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5.发明授权公开(公告)号：US07987339B2
公开(公告)日：2011-07-26
申请号：US12827416
申请日：2010-06-30
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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6.发明申请PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SELECTIVE DATA TRANSFER THROUGH COMMUNICATON ELEMENTS 有权使用通过通讯单元进行选择性数据传输的交互处理器的处理系统公开(公告)号：US20100229020A1
公开(公告)日：2010-09-09
申请号：US12781422
申请日：2010-05-17
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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7.发明申请STALL PROPAGATION IN A PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND COMMUNICATON ELEMENTS 有权在具有交互处理器和通信元素的处理系统中的延迟传播公开(公告)号：US20120102299A1
公开(公告)日：2012-04-26
申请号：US13341252
申请日：2011-12-30
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.
摘要翻译： 处理系统包括处理器和以散置的布置耦合在一起的动态可配置通信元件（DCC）。 源设备可以通过DCC的中间子集将数据项传送到目的地设备。 源和目的地设备可以各自对应于不同的处理器，DCC或输入/输出设备，或者它们的混合组合。 响应于在源设备开始将数据项传送到目的地设备之后并且在接收到目的地设备之前的所有数据项之前检测到停顿，停顿设备可操作以通过一个或多个 中间子集朝向源设备。 响应于接收到停止信息，中间子集中的至少一个可操作以缓冲数据项的全部或部分。
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8.发明授权Stall propagation in a processing system with interspersed processors and communicaton elements 有权在具有散置处理器和通信元素的处理系统中停滞传播公开(公告)号：US08478964B2
公开(公告)日：2013-07-02
申请号：US13341252
申请日：2011-12-30
IPC分类号： G06F9/00
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.
摘要翻译： 处理系统包括处理器和以散置的布置耦合在一起的动态可配置通信元件（DCC）。 源设备可以通过DCC的中间子集将数据项传送到目的地设备。 源和目的地设备可以各自对应于不同的处理器，DCC或输入/输出设备，或者它们的混合组合。 响应于在源设备开始将数据项传送到目的地设备之后并且在接收到目的地设备之前的所有数据项之前检测到停顿，停顿设备可操作以通过一个或多个 中间子集朝向源设备。 响应于接收到停止信息，中间子集中的至少一个可操作以缓冲数据项的全部或部分。
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9.发明申请PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SHARED MEMORY OF COMMUNICATION ELEMENTS 有权具有交互处理器的处理系统使用通信元件的共享存储器公开(公告)号：US20100228925A1
公开(公告)日：2010-09-09
申请号：US12781314
申请日：2010-05-17
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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10.发明授权Processing system with interspersed processors using selective data transfer through communication elements 有权具有穿插处理器的处理系统使用通过通信元件的选择性数据传输公开(公告)号：US08112612B2
公开(公告)日：2012-02-07
申请号：US12781422
申请日：2010-05-17
IPC分类号： G06F15/80
CPC分类号： G06F15/80 , G06F15/76 , G06F15/7867 , G06F15/8023 , Y02D10/12 , Y02D10/13
摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
摘要翻译： 一种处理系统，包括处理器和以散置的布置耦合在一起的动态可配置通信元件。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元素。
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