Coherent variable length reads from system memory
    3.
    发明授权
    Coherent variable length reads from system memory 失效
    相干可变长度读取系统内存

    公开(公告)号:US06298420B1

    公开(公告)日:2001-10-02

    申请号:US09567139

    申请日:2000-05-08

    IPC分类号: G06F1202

    摘要: Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

    摘要翻译: 当存储器控制器连接到流水线总线和串行总线时,用于在存储器控制器中处理串行总线读请求的方法和装置。 根据该方法,读取请求消息被接收并被分割成几个原子事务。 原子交易是在流水线上发行的。 与几个原子事务相关的数据存储在队列中。 请求的数据从队列中读取并放在串行总线上的响应消息中。