公开(公告)号：US08962411B2

公开(公告)日：2015-02-24

申请号：US13570253

申请日：2012-08-09

Applicant: Chien-An Yu ,  Yi-Fong Lin

Inventor： Chien-An Yu ,  Yi-Fong Lin

IPC: H01L21/337

CPC classification number: H01L27/10882 ,  H01L21/76224 ,  H01L27/1087 ,  H01L27/10876 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit pattern with high aspect ratio is disclosed. A plurality of parallel lines and supporting lines intersecting the parallel lines are formed. Supporting isolation structures are then formed in the space between the parallel lines and the supporting line for supporting the parallel lines in a later etching process. The parallel lines and the supporting line are then disconnected after the etching process.

Abstract translation: 公开了制造高纵横比的电路图案的方法。 形成与平行线交叉的多条平行线和支撑线。 然后在平行线和支撑线之间的空间中形成支撑隔离结构，用于在稍后的蚀刻工艺中支撑平行线。 然后在蚀刻过程之后将平行线和支撑线断开。

公开(公告)号：US20140041900A1

公开(公告)日：2014-02-13

申请号：US13570253

申请日：2012-08-09

Applicant: Chien-An Yu ,  Yi-Fong Lin

Inventor： Chien-An Yu ,  Yi-Fong Lin

IPC: H05K1/02 ,  H05K3/30 ,  H05K3/06

CPC classification number: H01L27/10882 ,  H01L21/76224 ,  H01L27/1087 ,  H01L27/10876 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit pattern with high aspect ratio is disclosed. A plurality of parallel lines and supporting lines intersecting the parallel lines are formed. Supporting isolation structures are then formed in the space between the parallel lines and the supporting line for supporting the parallel lines in a later etching process. The parallel lines and the supporting line are then disconnected after the etching process.

Abstract translation: 公开了制造高纵横比的电路图案的方法。 形成与平行线交叉的多条平行线和支撑线。 然后在平行线和支撑线之间的空间中形成支撑隔离结构，用于在稍后的蚀刻工艺中支撑平行线。 然后在蚀刻过程之后将平行线和支撑线断开。

公开(公告)号：US20130258743A1

公开(公告)日：2013-10-03

申请号：US13436980

申请日：2012-04-01

Applicant: Chien-An Yu ,  Yi-Fong Lin

Inventor： Chien-An Yu ,  Yi-Fong Lin

IPC: G11C5/06

CPC classification number: G11C7/18 ,  G11C11/4097 ,  H01L27/10885 ,  H01L27/10891

Abstract: A memory array includes a plurality of word lines extending along a first direction; a plurality of memory cells coupled to a first sub-bit line (SBL) extending along a second direction that is substantially orthogonal to the first direction; a first selector region disposed substantially in the middle of the first SBL thereby dividing the plurality of memory cells into two sub-groups, wherein the first selector region comprises at least one selector transistor that is coupled to the first SBL; and a main bit line (MBL) extending along the second direction and coupled to the selector transistor.

Abstract translation: 存储器阵列包括沿第一方向延伸的多个字线; 耦合到沿着基本上与第一方向正交的第二方向延伸的第一子位线（SBL）的多个存储单元; 第一选择器区域，其基本上设置在第一SBL的中间，从而将多个存储器单元分成两个子组，其中第一选择器区域包括耦合到第一SBL的至少一个选择晶体管; 以及沿着第二方向延伸并耦合到选择晶体管的主位线（MBL）。

公开(公告)号：US08536635B1

公开(公告)日：2013-09-17

申请号：US13469104

申请日：2012-05-11

Applicant: Chien-An Yu ,  Yuan-Sung Chang ,  Feng-Ling Chen ,  Chun-Hung Chien

Inventor： Chien-An Yu ,  Yuan-Sung Chang ,  Feng-Ling Chen ,  Chun-Hung Chien

IPC: H01L29/94

CPC classification number: H01L27/10885

Abstract: A semiconductor structure includes a semiconductor substrate having thereon a plurality of deep trenches and a plurality of pillar structures between the deep trenches, wherein each of the plurality of pillar structures comprises an upper portion and a lower portion. A doping region is formed in the lower portion. A diffusion barrier layer is disposed on a sidewall of the lower portion.

Abstract translation: 半导体结构包括其上具有多个深沟槽的半导体衬底和在深沟槽之间的多个柱结构，其中多个柱结构中的每一个包括上部和下部。 在下部形成掺杂区域。 扩散阻挡层设置在下部的侧壁上。

公开(公告)号：US20100001646A1

公开(公告)日：2010-01-07

申请号：US12487553

申请日：2009-06-18

Applicant: Chien-An YU ,  Pei-Chen Chen

Inventor： Chien-An YU ,  Pei-Chen Chen

IPC: B60Q1/04 ,  H02N2/18 ,  H05B37/02

CPC classification number: H02N2/18 ,  B62J6/06 ,  H05B33/0809

Abstract: A device capable of generating electricity includes a rotating unit and a piezoelectric component. The rotating unit is rotatable about a rotation axis and includes a plurality of strikers that are disposed at angularly spaced apart positions relative to the rotation axis and that define a plurality of voids, each of which is located between an adjacent pair of the strikers. The piezoelectric component has a portion that extends into one of the voids. Rotation of the rotating unit results in the strikers striking the portion of the piezoelectric component intermittently, and causes the piezoelectric component to deform, exhibit a direct piezoelectric effect and generate electricity.

Abstract translation: 能够发电的装置包括旋转单元和压电元件。 旋转单元可围绕旋转轴线旋转并且包括多个撞击器，其相对于旋转轴线以角度间隔开的位置设置并且限定多个空隙，每个空隙位于相邻的一对撞击器之间。 压电元件具有延伸到一个空隙中的部分。 旋转单元的旋转导致冲击器间歇地撞击压电元件的部分，并且使压电元件变形，呈现直接的压电效应并发电。

公开(公告)号：US20090148993A1

公开(公告)日：2009-06-11

申请号：US12055298

申请日：2008-03-25

Applicant: Chien-An Yu ,  Te-Yin Chen ,  Hai-Han Hung

Inventor： Chien-An Yu ,  Te-Yin Chen ,  Hai-Han Hung

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.

Abstract translation: 提供一种制造具有凹槽通道结构的半导体器件的方法。 在基板上形成第一凹部。 衬垫和填充层形成在第一凹部中。 与第一凹部相邻的衬底的一部分和衬垫的一部分和填充层被去除以形成沟槽。 绝缘层填充沟槽以形成隔离结构。 使用衬垫作为蚀刻停止层去除填充层，以露出绝缘层。 暴露的绝缘层的一部分被去除以形成具有与衬底的侧壁相邻的凸起的第二凹部。 衬里被移除。 介电层和栅极形成在覆盖第二凹槽的衬底上。 源极和漏极区域形成在与第二凹部相邻的衬底中。

公开(公告)号：US08699255B2

公开(公告)日：2014-04-15

申请号：US13436980

申请日：2012-04-01

Applicant: Chien-An Yu ,  Yi-Fong Lin

Inventor： Chien-An Yu ,  Yi-Fong Lin

IPC: G11C5/06

CPC classification number: G11C7/18 ,  G11C11/4097 ,  H01L27/10885 ,  H01L27/10891

Abstract: A memory array includes a plurality of word lines extending along a first direction; a plurality of memory cells coupled to a first sub-bit line (SBL) extending along a second direction that is substantially orthogonal to the first direction; a first selector region disposed substantially in the middle of the first SBL thereby dividing the plurality of memory cells into two sub-groups, wherein the first selector region comprises at least one selector transistor that is coupled to the first SBL; and a main bit line (MBL) extending along the second direction and coupled to the selector transistor.

Abstract translation: 存储器阵列包括沿第一方向延伸的多个字线; 耦合到沿着基本上与第一方向正交的第二方向延伸的第一子位线（SBL）的多个存储单元; 第一选择器区域，其基本上设置在第一SBL的中间，从而将多个存储器单元分成两个子组，其中第一选择器区域包括耦合到第一SBL的至少一个选择晶体管; 以及沿着第二方向延伸并耦合到选择晶体管的主位线（MBL）。

公开(公告)号：US20050054204A1

公开(公告)日：2005-03-10

申请号：US10727846

申请日：2003-12-04

Applicant: Chien-An Yu

Inventor： Chien-An Yu

IPC: H01L21/308 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L21/308 ,  H01L21/76235

Abstract: A method for rounding the top corner of a trench. A masking layer is formed on a substrate, and the masking layer is then patterned to form at least one opening therein to expose the substrate and form a recess region in the substrate. The recess region is oxidized to form a first oxide layer to round the top corner of the recess region. The first oxide layer and the substrate under the opening are successively etched to form a trench in the substrate. A second oxide layer is conformably formed on the surface of the trench. A method for forming a shallow trench isolation structure is also disclosed.

Abstract translation: 一种用于使沟槽顶角倒圆的方法。 在衬底上形成掩模层，然后对掩模层进行图案化以在其中形成至少一个开口以暴露衬底并在衬底中形成凹陷区域。 凹陷区域被氧化以形成第一氧化物层以围绕凹陷区域的顶角。 依次蚀刻第一氧化物层和开口下的衬底，以在衬底中形成沟槽。 在沟槽的表面上顺应地形成第二氧化物层。 还公开了一种形成浅沟槽隔离结构的方法。

公开(公告)号：US20140252459A1

公开(公告)日：2014-09-11

申请号：US13792228

申请日：2013-03-11

Applicant: Chien-An Yu ,  Yuan-Sung Chang ,  Yi-Fong Lin ,  Chin-Piao Chang ,  Chih-Huang Wu ,  Wen-Chieh Wang

Inventor： Chien-An Yu ,  Yuan-Sung Chang ,  Yi-Fong Lin ,  Chin-Piao Chang ,  Chih-Huang Wu ,  Wen-Chieh Wang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10891 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/7827

Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region.

Abstract translation: 提供一种制造半导体器件的方法，其包括以下步骤。 提供具有多个支柱的基板，其中围绕每个支柱形成多个沟槽，并且掺杂区域设置在每个支柱的底部。 在每个掺杂区域之下形成绝缘层。

公开(公告)号：US07696075B2

公开(公告)日：2010-04-13

申请号：US12055298

申请日：2008-03-25

Applicant: Chien-An Yu ,  Te-Yin Chen ,  Hai-Han Hung

Inventor： Chien-An Yu ,  Te-Yin Chen ,  Hai-Han Hung

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/78 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.

Abstract translation: 提供一种制造具有凹槽通道结构的半导体器件的方法。 在基板上形成第一凹部。 衬垫和填充层形成在第一凹部中。 与第一凹部相邻的衬底的一部分和衬垫的一部分和填充层被去除以形成沟槽。 绝缘层填充沟槽以形成隔离结构。 使用衬垫作为蚀刻停止层去除填充层，以露出绝缘层。 暴露的绝缘层的一部分被去除以形成具有与衬底的侧壁相邻的凸起的第二凹部。 衬里被移除。 介电层和栅极形成在覆盖第二凹槽的衬底上。 源极和漏极区域形成在与第二凹部相邻的衬底中。