公开(公告)号：US06767821B1

公开(公告)日：2004-07-27

申请号：US10426354

申请日：2003-04-07

Applicant: Chan-syun David Yang ,  Ajay Kumar ,  Wei-Te Wu ,  Changhun Lee ,  Yeajer Arthur Chen ,  Katsuhisa Kugimiya

Inventor： Chan-syun David Yang ,  Ajay Kumar ,  Wei-Te Wu ,  Changhun Lee ,  Yeajer Arthur Chen ,  Katsuhisa Kugimiya

IPC: H01L214763

CPC classification number: H01L21/32137 ,  H01L21/32139 ,  H01L21/76838 ,  Y10S438/945

Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.

Abstract translation: 制造互连线的方法包括形成壁，沉积具有朝向壁底部减小的厚度的蚀刻掩模，以及在底部各向同性蚀刻壁，以形成在衬底之间具有预定间隙的互连线 和底线。

公开(公告)号：US06209551B1

公开(公告)日：2001-04-03

申请号：US08873611

申请日：1997-06-11

Applicant: Chan-Syun David Yang ,  Yun-Yen Jack Yang

Inventor： Chan-Syun David Yang ,  Yun-Yen Jack Yang

IPC: H01L21302

CPC classification number: H01L21/02071

Abstract: Methods and compositions for treating a wafer's layer stack following metal etching are provided. The methods involve providing a semiconductor wafer layer stack in a plasma processing system following metal etch, and treating the layer stack with one or more process gases in a plasma processing system, where at least one of the process gases contains helium and water and/or oxygen, or comparable gases. The methods and compositions reduce corrosion and polymer fence for a wafer's layer stack relative to conventional passivation and strip processes without helium, decrease the time necessary for passivation, increase the strip rate, and/or improve strip uniformity.

Abstract translation: 提供了在金属蚀刻之后处理晶片层堆叠的方法和组合物。 所述方法包括在金属蚀刻之后的等离子体处理系统中提供半导体晶片层堆叠，以及在等离子体处理系统中用一种或多种工艺气体处理层叠层，其中至少一种处理气体包含氦和水和/或 氧气或类似气体。 相对于没有氦的常规钝化和剥离过程，这些方法和组合物减少了晶片层叠的腐蚀和聚合物栅栏，减少了钝化所需的时间，增加了带材速率和/或改善了带材均匀性。

公开(公告)号：US06759340B2

公开(公告)日：2004-07-06

申请号：US10143269

申请日：2002-05-09

Applicant: Padmapani C. Nallan ,  Ajay Kumar ,  Anisul H. Khan ,  Chan-Syun David Yang

Inventor： Padmapani C. Nallan ,  Ajay Kumar ,  Anisul H. Khan ,  Chan-Syun David Yang

IPC: H01L21302

CPC classification number: H01L21/30655

Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

Abstract translation: 本文公开了一种在覆盖电介质材料的硅中蚀刻沟槽的方法，其减小或基本上消除在沟槽的基部处的凹口，同时减少沟槽侧壁上的扇形。 该方法包括通过将硅衬底通过图案化掩模层暴露于由含氟气体产生的等离子体来蚀刻沟槽的第一部分。 该蚀刻之后是聚合物沉积步骤，包括将衬底暴露于由能够在蚀刻的硅表面上形成聚合物的气体产生的等离子体。 根据沟槽第一部分的期望深度，蚀刻和聚合物沉积步骤重复多个循环。 通过将硅暴露于由含氟气体和聚合物形成气体的组合产生的等离子体来蚀刻沟槽的最后部分。

公开(公告)号：US06551941B2

公开(公告)日：2003-04-22

申请号：US09791446

申请日：2001-02-22

Applicant: Chan-syun David Yang ,  Meihua Shen ,  Oranna Yauw ,  Jeffrey D. Chinn

Inventor： Chan-syun David Yang ,  Meihua Shen ,  Oranna Yauw ,  Jeffrey D. Chinn

IPC: H01L2100

CPC classification number: H01L21/32137 ,  H01L21/28114 ,  H01L21/28123

Abstract: A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls. The remaining portion of the silicon-containing gate layer is etched at a lower bias power using a plasma generated from a second source gas which selectively etches the silicon-containing gate layer relative to the underlying gate dielectric layer, whereby a lower sidewall of the silicon-containing gate layer is formed and an upper surface of the gate dielectric layer is exposed. The etch stack is then exposed to a plasma generated from a third source gas which includes nitrogen, whereby a second, nitrogen-containing passivation layer is formed on the exposed sidewalls of the silicon-containing gate layer. Subsequently, a notch is etched in the lower sidewall of the silicon-containing gate layer. The method of the invention provides control over both the height and the width of the notch, while providing a marked improvement in notch critical dimension uniformity between isolated and dense feature areas of the substrate.

Abstract translation: 公开了一种形成缺口含硅栅极结构的方法。 该方法在形成T形含硅栅极结构中特别有用。 使用从第一源气体产生的等离子体将含硅栅极层蚀刻到第一期望深度。 在蚀刻期间，蚀刻副产物沉积在蚀刻期间暴露的含硅栅极层的上侧壁上，形成第一钝化层，其在随后的处理步骤期间保护上部含硅栅极层侧壁免受蚀刻。 在该第一蚀刻步骤期间使用相对较高的衬底偏置功率以确保钝化层适当地粘附到上部含硅栅极侧壁。 使用从第二源气体产生的等离子体以较低的偏置功率蚀刻剩余部分的含硅栅极层，该等离子体选择性地相对于下面的栅介质层蚀刻含硅栅极层，由此硅的下侧壁 形成栅极层，并且露出栅极电介质层的上表面。 然后将蚀刻堆叠暴露于由包括氮的第三源气体产生的等离子体，由此在含硅栅极层的暴露的侧壁上形成第二含氮钝化层。 随后，在含硅栅极层的下侧壁蚀刻凹口。 本发明的方法提供对凹口的高度和宽度的控制，同时提供了衬底的隔离和致密特征区域之间的切口临界尺寸均匀性的显着改进。