公开(公告)号：US06907520B2

公开(公告)日：2005-06-14

申请号：US10044487

申请日：2002-01-11

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F9/00 ,  G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3885 ,  G06F12/0862

摘要： A method and apparatus for predicting load addresses and identifying new threads of instructions for execution in a multithreaded processor. A load prediction unit scans an instruction window for load instructions. A load prediction table is searched for an entry corresponding to a detected load instruction. If an entry is found in the table, a load address prediction is made for the load instruction and conveyed to the data cache. If the load address misses in the cache, the data is prefetched. Subsequently, if it is determined that the load prediction was incorrect, a miss counter in the corresponding entry in the load prediction table is incremented. If on a subsequent detection of the load instruction, the miss counter has reached a threshold, the load instruction is predicted to miss. In response to the predicted miss, a new thread of instructions is identified for execution.

摘要翻译： 一种用于预测负载地址并识别用于在多线程处理器中执行的指令的新线程的方法和装置。 负载预测单元扫描指令窗口以进行加载指令。 搜索负载预测表与对应于检测到的加载指令的条目。 如果在表中找到条目，则对加载指令进行加载地址预测并传送到数据高速缓存。 如果缓存中的加载地址丢失，则预取数据。 随后，如果确定负载预测不正确，则负载预测表中的相应条目中的未命中计数器增加。 如果随后检测到加载指令，则未命中计数器已经达到阈值，预计加载指令将错过。 响应于预测的错误，识别出新的指令线程用于执行。

公开(公告)号：US6115756A

公开(公告)日：2000-09-05

申请号：US883862

申请日：1997-06-27

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F15/16 ,  G06F13/00 ,  H04L12/46 ,  G06F15/173

CPC分类号： H04L12/4637

摘要： A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and the modules are coupled to one or more rings. Bridge modules may be included for transmitting between rings in the hierarchy. The rings are time division multiplexed, and each time slot on a ring carries a frame. According to an address carried within the frame, bridge modules determine whether or not to transmit a frame circulating on a source ring onto a target ring. If the address of the frame indicates a module upon the source ring, the bridge module retransmits the frame on the source ring. Otherwise, the bridge module transmits the frame on the target ring. The bridge module operates in this fashion at any level of the hierarchy. The owner of a time slot on a ring is permitted to release the time slot for use by other modules. To reclaim a time slot, the owner marks the time slot owned. The module using the time slot, upon detecting the owned mark, removes the frame from the time slot and responds with a null frame. If a module detects a frame to which that module is to respond but the module's buffer is full, the module may retransmit the frame upon the source ring. The time slot carrying the frame effectively serves as a queue position. According to one embodiment, rings comprise optical links.

摘要翻译： 计算机系统采用分层环结构进行通信。 计算机系统元件配置为具有环形接口硬件的模块，并且模块耦合到一个或多个环。 可以包括桥模块以在层次结构中的环之间进行传输。 环是时分复用的，环上的每个时隙都携带一个帧。 根据帧内携带的地址，桥模块确定是否将在源环上循环的帧发送到目标环上。 如果帧的地址指示源环上的模块，则桥模块将重传源环上的帧。 否则，桥模块将目标环上的帧传输。 桥模块以这种方式在层次结构的任何级别上操作。 允许环上的时隙的拥有者释放其他模块使用的时隙。 要收回时隙，所有者标记所属的时隙。 使用时隙的模块在检测到拥有的标记时，从时隙中移除帧，并以空帧进行响应。 如果模块检测到该模块要响应的帧，但模块的缓冲区已满，则模块可能会在源环上重新发送帧。 携带帧的时隙有效地用作队列位置。 根据一个实施例，环包括光学链路。

公开(公告)号：US5812816A

公开(公告)日：1998-09-22

申请号：US806860

申请日：1997-02-26

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/08 ,  G06F12/0897

摘要： A system and method for transferring data over a dedicated memory transfer bus between high and low speed memories of a computer system which share a single real memory address space are disclosed. The dedicated memory transfer bus operates independently from the system bus to avoid any adverse effects on bandwidth and latency of the system bus and to allow virtually any memory hierarchy to be selected. The transfer is controlled by the operating system software upon the execution of instructions issued by the memory management unit. Status information such as "invalid" state is used to direct the transfer.

摘要翻译： 公开了一种用于在共享单个真实存储器地址空间的计算机系统的高速和低速存储器之间通过专用存储器传输总线传送数据的系统和方法。 专用存储器传输总线独立于系统总线工作，以避免对系统总线的带宽和延迟的任何不利影响，并允许实际上选择任何存储器层级。 在执行由存储器管理单元发出的指令时，由操作系统软件控制传送。 诸如“无效”状态的状态信息用于指示传送。

公开(公告)号：US6055613A

公开(公告)日：2000-04-25

申请号：US928221

申请日：1997-09-12

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/08 ,  G06F12/0897

摘要： A system and method for transferring data over a dedicated memory transfer bus between high and low speed memories of a computer system which share a single real memory address space are disclosed. The dedicated memory transfer bus operates independently from the system bus to avoid any adverse effects on bandwidth and latency of the system bus and to allow virtually any memory hierarchy to be selected. The transfer is controlled by the operating system software upon the execution of instructions issued by the memory management unit. Status information such as "invalid" state is used to direct the transfer.

摘要翻译： 公开了一种用于在共享单个真实存储器地址空间的计算机系统的高速和低速存储器之间通过专用存储器传输总线传送数据的系统和方法。 专用存储器传输总线独立于系统总线工作，以避免对系统总线的带宽和延迟的任何不利影响，并允许实际上选择任何存储器层级。 在执行由存储器管理单元发出的指令时，由操作系统软件控制传送。 诸如“无效”状态的状态信息用于指示传送。

公开(公告)号：US6006320A

公开(公告)日：1999-12-21

申请号：US234584

申请日：1999-01-21

申请人： Bodo K Parady

发明人： Bodo K Parady

IPC分类号： G06F9/38 ,  G06F9/50 ,  G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3851 ,  G06F9/5011 ,  G06F2209/5011 ,  G06F2209/507

摘要： A processor that includes hardware resources for the operating system that are separate and independent from resources dedicated to user programs. The OS resources preferably include a separate OS arithmetic logic unit (OS/ALU) along with a dedicated instruction buffer, instruction cache and data cache. The OS/ALU is preferably able to control the registers and program address of user processes, and can read a program request register from the user program.

摘要翻译： 一种处理器，其包括与专用于用户程序的资源分开独立的操作系统的硬件资源。 OS资源优选地包括单独的OS算术逻辑单元（OS / ALU）以及专用指令缓冲器，指令高速缓存和数据高速缓存。 OS / ALU优选地能够控制用户进程的寄存器和程序地址，并且可以从用户程序读取程序请求寄存器。

公开(公告)号：US5649143A

公开(公告)日：1997-07-15

申请号：US459755

申请日：1995-06-02

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1045

摘要： Logic circuitry and a corresponding method for computing an indexed set address utilized by a cache to mitigate the probability of a conflict miss occurring for a given memory access. Implemented at component or system level, the logic circuitry performs pseudo-random indexing of a set address obtained from a memory address during a memory access by a processor unit. This is accomplished by performing operations consistent with modulo operations on the memory address.

摘要翻译： 逻辑电路和用于计算高速缓存使用的索引集合地址以减轻针对给定存储器访问发生冲突异常的概率的相应方法。 在组件或系统级实施，逻辑电路在由处理器单元进行的存储器访问期间对从存储器地址获得的集合地址执行伪随机索引。 这通过执行与存储器地址上的模运算一致的操作来实现。

公开(公告)号：US06859844B2

公开(公告)日：2005-02-22

申请号：US10079294

申请日：2002-02-20

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F15/16 ,  G06F13/00 ,  H04L12/46 ,  H04B7/212

CPC分类号： H04L12/4637

摘要： A computer system comprises a plurality of modules and a shift register having a plurality of slots connected in series, wherein each of the plurality of slots is coupled to one of the plurality of modules. In one embodiment, an output of a last slot of the plurality of slots is coupled to an input of an initial slot of the plurality of slots to form a ring. Each slot of the shift register corresponds to a time slot on the ring, and each of the time slots is assigned to one of the modules. At least two of the modules are configured to independently generate frames for transmission on the ring. In another embodiment, at least one of the modules comprises a bridge module coupled to communicate with other bridge modules separate from the plurality of modules.

摘要翻译： 计算机系统包括多个模块和移位寄存器，该移位寄存器具有串联连接的多个槽，其中多个槽中的每一个与多个模块中的一个耦合。 在一个实施例中，多个时隙中的最后时隙的输出被耦合到多个时隙的初始时隙的输入以形成一个环。 移位寄存器的每个时隙对应于环上的时隙，并且每个时隙被分配给其中一个模块。 至少两个模块被配置为独立地生成用于在环上传输的帧。 在另一个实施例中，模块中的至少一个包括桥模块，桥模块耦合以与与多个模块分离的其它桥模块通信。

公开(公告)号：US06578137B2

公开(公告)日：2003-06-10

申请号：US09925090

申请日：2001-08-08

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F940

CPC分类号： G06F9/462 ,  G06F9/3851 ,  G06F9/3861

摘要： A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

摘要翻译： 一种用于响应于长延迟事件来切换程序的线程的方法和装置。 在一个实施例中，长延迟事件是加载或存储操作，如果在2级高速缓存中存在未命中则触发线程切换。 除了为多个线程提供单独的寄存器组之外，还提供了指向不同线程的一组程序地址寄存器。 切换机制响应长时延事件在程序地址寄存器之间切换。

公开(公告)号：US06437653B1

公开(公告)日：2002-08-20

申请号：US09675115

申请日：2000-09-28

申请人： Jose M. Cruz ,  Bodo K. Parady

发明人： Jose M. Cruz ,  Bodo K. Parady

IPC分类号： H03B512

CPC分类号： H01L23/645 ,  H01F17/0006 ,  H01F21/08 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： One embodiment of the present invention provides an inductor with a variable inductance within a semiconductor chip. This inductor includes a primary spiral composed of a conductive material embedded within the semiconductor chip to provide a source of variable inductance. It also includes a control spiral composed of the conductive material vertically displaced from the primary spiral in neighboring layers of the semiconductor chip. This control spiral is magnetically coupled with the primary spiral so that changing a control current through the control spiral induces a change in inductance through the primary spiral. The inductor also includes a controllable current source coupled to the control spiral that is configured to provide the control current. One embodiment of the present invention includes a core surrounding the primary spiral and the control spiral in the semiconductor chip. This core is comprised of a core material with a magnetic permeability that facilitates magnetically coupling the control spiral with the primary spiral. In a variation on this embodiment, the core material includes a high frequency ferrite that operates at a frequency above one gigahertz without resistive eddy losses that substantially prevent a magnetic coupling between the control spiral and the primary spiral. In a variation on this embodiment, the high frequency ferrite can include NiZn.

摘要翻译： 本发明的一个实施例提供一种在半导体芯片内具有可变电感的电感器。 该电感器包括由嵌入在半导体芯片内的导电材料构成的初级螺旋，以提供可变电感源。 它还包括由半导体芯片的相邻层中与主螺旋垂直偏移的导电材料组成的控制螺旋。 该控制螺旋与初级螺旋磁耦合，使得通过控制螺旋改变控制电流通过初级螺旋引起电感的变化。 电感器还包括耦合到被配置为提供控制电流的控制螺旋的可控电流源。 本发明的一个实施例包括围绕初级螺旋的芯和半导体芯片中的控制螺旋。 该芯由具有磁导率的芯材组成，其有助于将控制螺旋与主螺旋磁耦合。 在该实施例的变型中，芯材料包括在高于1千兆赫兹的频率下工作的高频铁氧体，而没有电阻涡流损耗，其基本上防止了控制螺旋和初级螺旋之间的磁耦合。 在本实施例的变型中，高频铁氧体可以包括NiZn。

公开(公告)号：US06385657B1

公开(公告)日：2002-05-07

申请号：US09553600

申请日：2000-04-20

申请人： Bodo K. Parady

发明人： Bodo K. Parady

IPC分类号： G06F1516

CPC分类号： H04L12/4637

摘要： A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and the modules are coupled to one or more rings. Bridge modules may be included for transmitting between rings in the hierarchy. The rings are time division multiplexed, and each time slot on a ring carries a frame. According to an address carried within the frame, bridge modules determine whether or not to transmit a frame circulating on a source ring onto a target ring. If the address of the frame indicates a module upon the source ring, the bridge module retransmits the frame on the source ring. Otherwise, the bridge module transmits the frame on the target ring. The bridge module operates in this fashion at any level of the hierarchy. The owner of a time slot on a ring is permitted to release the time slot for use by other modules. To reclaim a time slot, the owner marks the time slot owned. The module using the time slot, upon detecting the owned mark, removes the frame from the time slot and responds with a null frame. If a module detects a frame to which that module is to respond but the module's buffer is full, the module may retransmit the frame upon the source ring. The time slot carrying the frame effectively serves as a queue position. According to one embodiment, rings comprise optical links.

摘要翻译： 计算机系统采用分层环结构进行通信。 计算机系统元件配置为具有环形接口硬件的模块，并且模块耦合到一个或多个环。 可以包括桥模块以在层次结构中的环之间进行传输。 环是时分复用的，环上的每个时隙都携带一个帧。 根据帧内携带的地址，桥模块确定是否将在源环上循环的帧发送到目标环上。 如果帧的地址指示源环上的模块，则桥模块将重传源环上的帧。 否则，桥模块将目标环上的帧传输。 桥模块以这种方式在层次结构的任何级别上操作。 允许环上的时隙的拥有者释放其他模块使用的时隙。 要收回时隙，所有者标记所属的时隙。 使用时隙的模块在检测到拥有的标记时，从时隙中移除帧，并以空帧进行响应。 如果模块检测到该模块要响应的帧，但模块的缓冲区已满，则模块可能会在源环上重新发送帧。 携带帧的时隙有效地用作队列位置。 根据一个实施例，环包括光学链路。