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公开(公告)号：US08959131B2
公开(公告)日：2015-02-17
申请号：US13137950
申请日：2011-09-22
CPC分类号： G06F5/00 , G06F7/483 , G06F7/499 , G06F7/49963 , G06F9/30014 , G06F9/30025 , G06F2207/382 , H03M7/24
摘要： Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantize and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.
摘要翻译： 用于处理数据的装置包括用于解码程序指令的处理电路16,18,20,22,24,26和解码器电路14。 所解码的程序指令包括一个浮点预转换指令，其执行圆到最近的连接，以便在输入浮点数的尾数字上偶数舍入以产生具有相同尾数长度但尾数四舍五入的输出浮点数 对应于较短的尾数字段的位置。 输出尾数字段包括将值的后缀连接在舍入值上。 用于电路14的解码器还响应于整数预转换指令来量化和输入整数值，使用到最近的连带到偶数舍入以形成输出整数操作数，其具有匹配到的尾数大小的有效位数 使用整数到浮点转换指令后续整数的浮点数。
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公开(公告)号：US09927882B2
公开(公告)日：2018-03-27
申请号：US13459347
申请日：2012-04-30
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/023 , G06F3/0489 , G08C17/00 , H04N5/44 , H04N21/426 , G09G5/36
CPC分类号： G06F3/0238 , G06F3/0489 , G08C17/00 , G09G5/363 , H04N5/4403 , H04N21/42653 , H04N2005/4441
摘要： A graphics processing unit 2 includes a texture pipeline 6 having a first pipeline portion 18 and a second pipeline portion 20. A subject instruction within the first pipeline portion 18 is recirculated within the first pipeline portion 18 until descriptor data to be loaded from a memory 4 by that subject instruction has been cached within a shared descriptor cache 22. When the descriptor has been stored within the shared descriptor cache 22, then the subject instruction is passed to the second pipeline portion 20 where further processing operations are performed and the subject instruction recirculated until those further processing operations have completed. The descriptor data is locked within the shared descriptor cache 22 until there are no pending subject instructions within the texture pipeline 6 which required to use that descriptor data.
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公开(公告)号：US20120303900A1
公开(公告)日：2012-11-29
申请号：US13459347
申请日：2012-04-30
CPC分类号： G06F3/0238 , G06F3/0489 , G08C17/00 , G09G5/363 , H04N5/4403 , H04N21/42653 , H04N2005/4441
摘要： A graphics processing unit 2 includes a texture pipeline 6 having a first pipeline portion 18 and a second pipeline portion 20. A subject instruction within the first pipeline portion 18 is recirculated within the first pipeline portion 18 until descriptor data to be loaded from a memory 4 by that subject instruction has been cached within a shared descriptor cache 22. When the descriptor has been stored within the shared descriptor cache 22, then the subject instruction is passed to the second pipeline portion 20 where further processing operations are performed and the subject instruction recirculated until those further processing operations have completed. The descriptor data is locked within the shared descriptor cache 22 until there are no pending subject instructions within the texture pipeline 6 which required to use that descriptor data.
摘要翻译： 图形处理单元2包括具有第一流水线部分18和第二流水线部分20的纹理流水线6.第一流水线部分18内的主题指令在第一流水线部分18内再循环，直到从存储器4加载的描述符数据 通过该主体指令已经被缓存在共享描述符高速缓存22中。当描述符已经被存储在共享描述符高速缓存22中时，则该主题指令被传递到第二流水线部分20，其中执行进一步的处理操作， 直到那些进一步的处理操作完成。 描述符数据被锁定在共享描述符高速缓存22中，直到纹理流水线6内没有待使用该描述符数据的待处理主题指令为止。
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4.发明申请Control of entry of program instructions to a fetch stage within a processing pipepline 有权将程序指令输入到处理流水线内的提取阶段的控制公开(公告)号：US20120137076A1
公开(公告)日：2012-05-31
申请号：US12926600
申请日：2010-11-29
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F9/3802 , G06F9/3814
摘要： A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation circuitry within the main query stage 20 and within a buffer query stage 26 serve to concurrently generate a main query request and a buffer query request sent to the cache memory 14. The cache memory returns a main query response and a buffer query response. Arbitration circuitry 28 controls multiplexers 30, 32 and 34 to direct the program instruction at the main query stage 20, and the program instruction stored within the buffer 24 and the buffer query stage 26 to pass either to the fetch stage 22 or to the buffer 24. The multiplexer 30 can also select a new instruction to be passed to the main query stage 20.
摘要翻译： 处理流水线6,8,10,12具有主查询级20和读取级22.缓冲器24存储已经错过高速缓冲存储器14内的程序指令。主查询级20内和内查询级内的查询生成电路 缓冲器查询阶段26用于同时产生发送到高速缓存存储器14的主查询请求和缓冲查询请求。高速缓冲存储器返回主查询响应和缓冲查询响应。 仲裁电路28控制多路复用器30,32和34以指导主查询阶段20处的程序指令，以及存储在缓冲器24和缓冲器查询阶段26内的程序指令，以通过读取级22或缓冲器24 复用器30还可以选择要传递到主查询级20的新指令。
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5.发明授权Control of entry of program instructions to a fetch stage within a processing pipepline 有权将程序指令输入到处理流水线内的提取阶段的控制公开(公告)号：US08977815B2
公开(公告)日：2015-03-10
申请号：US12926600
申请日：2010-11-29
CPC分类号： G06F12/0855 , G06F9/3802 , G06F9/3814
摘要： A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation circuitry within the main query stage 20 and within a buffer query stage 26 serve to concurrently generate a main query request and a buffer query request sent to the cache memory 14. The cache memory returns a main query response and a buffer query response. Arbitration circuitry 28 controls multiplexers 30, 32 and 34 to direct the program instruction at the main query stage 20, and the program instruction stored within the buffer 24 and the buffer query stage 26 to pass either to the fetch stage 22 or to the buffer 24. The multiplexer 30 can also select a new instruction to be passed to the main query stage 20.
摘要翻译： 处理流水线6,8,10,12具有主查询级20和读取级22.缓冲器24存储已经错过高速缓冲存储器14内的程序指令。主查询级20内和内查询级内的查询生成电路 缓冲器查询阶段26用于同时产生发送到高速缓存存储器14的主查询请求和缓冲查询请求。高速缓冲存储器返回主查询响应和缓冲查询响应。 仲裁电路28控制多路复用器30,32和34以指导主查询阶段20处的程序指令，以及存储在缓冲器24和缓冲器查询阶段26内的程序指令，以通过读取级22或缓冲器24 复用器30还可以选择要传递到主查询级20的新指令。
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公开(公告)号：US20120254882A1
公开(公告)日：2012-10-04
申请号：US13064598
申请日：2011-04-01
IPC分类号： G06F9/46
CPC分类号： G06F9/54 , G06F9/3851 , G06F9/3859 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
摘要翻译： 数据处理装置包括处理电路，其布置成使用处理电路可访问的资源来处理处理线程。 提供管线用于处理待处理电路等待处理的至少两个待处理线程。 流水线包括至少一个资源请求流水线级，用于请求访问待处理线程的资源。 优先级控制器控制待处理线程的优先级。 优先级定义优先级，通过该优先级等待线程授予对资源的访问权限。 当待处理线程达到最终流水线阶段时，如果请求资源不可用，则该线程的优先级级别被有选择地提升，并且该线程返回到流水线的第一流水线级。 如果所请求的资源可用，则线程将从管道转发。
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公开(公告)号：US20120215822A1
公开(公告)日：2012-08-23
申请号：US13137950
申请日：2011-09-22
IPC分类号： G06F7/483
CPC分类号： G06F5/00 , G06F7/483 , G06F7/499 , G06F7/49963 , G06F9/30014 , G06F9/30025 , G06F2207/382 , H03M7/24
摘要： Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.
摘要翻译： 用于处理数据的装置包括用于解码程序指令的处理电路16,18,20,22,24,26和解码器电路14。 所解码的程序指令包括一个浮点预转换指令，其执行圆到最近的连接，以便在输入浮点数的尾数字上偶数舍入以产生具有相同尾数长度但尾数四舍五入的输出浮点数 对应于较短的尾数字段的位置。 输出尾数字段包括将值的后缀连接在舍入值上。 用于电路14的解码器还响应于整数预转换指令，以使用向量到最近的系数对偶数舍入进行定量和输入整数值，以形成输出整数运算数，该输出整数运算符的数目与 使用整数到浮点转换指令后续整数的浮点数。
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公开(公告)号：US20090198893A1
公开(公告)日：2009-08-06
申请号：US12068009
申请日：2008-01-31
CPC分类号： G06F12/1027
摘要： A memory management arrangement includes a memory management unit 1, a cache memory 2 and a queue arrangement 3. The queue 3 is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit 1 via the bus 5 for retrying through the memory management unit at a later time.If a memory access request sent to the memory management unit 1 experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache 2, the memory management unit 1 operates to place the failed memory access request in the replay queue 3, and allows subsequent memory access requests to continue.The failed memory access requests in the queue 3 are then continuously circulated through the memory management unit 1 from the queue alternately with new memory access requests from other access initiators 4.
摘要翻译： 存储器管理装置包括存储器管理单元1，高速缓存存储器2和队列装置3.队列3是先入先出（FIFO）缓冲器，其可以排队失败的存储器访问请求并将其作为输入返回 存储器管理单元1经由总线5用于稍后再次通过存储器管理单元重试。 如果发送到存储器管理单元1的存储器访问请求经历高速缓存“未命中”，则代替阻塞存储器访问请求直到所需地址数据已经被加载到高速缓存2中，存储器管理单元1操作以将故障存储器存取 重播队列3中的请求，并允许后续内存访问请求继续。 队列3中的故障存储器访问请求随后从其他访问发起者4与来自队列的新存储器访问请求交替地通过存储器管理单元1循环。
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公开(公告)号：US08766991B2
公开(公告)日：2014-07-01
申请号：US13067342
申请日：2011-05-25
CPC分类号： G06F12/0802 , G06T1/20 , G09G5/39
摘要： A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the texture pipeline in a variable order corresponding to the order in which they are retrieved from a memory 4. If the texture values are floating point texture values, then they are processed in a fixed order in order to ensure result invariants as the filter operation is non-associative for floating point values. The filter operation is not commenced until all of the floating point texture values have been retrieved from the memory 4 and other available for processing.
摘要翻译： 图形处理单元2包括对纹理值执行滤波操作的纹理管线6。 如果纹理值是整数纹理值，则它们可以由纹理流水线以与从存储器4检索的顺序相对应的可变顺序来处理。如果纹理值是浮点纹理值，则它们被处理 以固定顺序，以确保结果不变量，因为过滤器操作对于浮点值是非关联的。 过滤器操作不会开始，直到从存储器4检索到所有浮点纹理值，并且可以处理的其他值。
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10.发明授权Data processing apparatus and method for processing a received workload in order to generate result data 有权用于处理所接收的工作负载以便生成结果数据的数据处理装置和方法公开(公告)号：US08601485B2
公开(公告)日：2013-12-03
申请号：US13067341
申请日：2011-05-25
IPC分类号： G06F9/46
CPC分类号： G06F9/46 , G06F9/4881 , G06F2209/483 , G06F2209/484 , G06T1/20 , Y02D10/24
摘要： A data processing apparatus and method are provided for processing a received workload in order to generate result data. A thread group generator generates from the received workload a plurality of thread groups to be executed to process the received workload. Each thread may be either an active thread whose output is required to form the result data, or a dummy thread required to resolve the inter-thread dependency for one of the active threads but whose output is not required to form the result data. Execution flow modification circuitry is responsive to the received thread group having at least one dummy thread, to cause the thread execution unit to selectively omit at least part of the execution of at least one of the plurality of instructions when executing each dummy thread, in dependence on control information associated with the predetermined program.
摘要翻译： 提供了一种数据处理装置和方法，用于处理所接收的工作负载以产生结果数据。 线程组生成器从接收到的工作负载生成要执行的多个线程组以处理所接收的工作负载。 每个线程可以是要求其输出来形成结果数据的活动线程，也可以是解决对其中一个活动线程但不需要输出结果数据的线程间依赖性所需的虚拟线程。 执行流修改电路响应于具有至少一个虚拟线程的所接收的线程组，以使得线程执行单元在执行每个虚拟线程时有选择地省略至少一部分执行多条指令，依赖 关于与预定程序相关联的控制信息。
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