公开(公告)号：US20150186328A1

公开(公告)日：2015-07-02

申请号：US14142812

申请日：2013-12-28

Applicant: Nadav Bonen ,  Alexey Kostinsky

Inventor： Nadav Bonen ,  Alexey Kostinsky

IPC: G06F13/42 ,  G06F1/28

CPC classification number: G11C29/022 ,  G11C7/02 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A system avoids false sampling due to reflections from previous commands or other noise on a data strobe line. The system uses a normalizer circuit or leaker circuit, and the data strobe line is not optimally terminated or is unterminated. The data strobe line is to receive a burst of data sample pulses or edges and sample a data line based on the edges. The receiving device includes logic that generates a count triggered from an initial edge on the data strobe line, and identifies, based on the count, an initial valid edge of the burst. Any false strobes due to noise or reflections that are received prior to the actual burst can be rejected.

Abstract translation: 系统避免了由于先前命令的反射或数据选通线上的其他噪声导致的错误采样。 系统使用归一化电路或漏电电路，数据选通线不是最终终止或未终止。 数据选通线是接收脉冲数据采样脉冲或边缘，并根据边沿采样数据线。 接收设备包括产生从数据选通线上的初始边缘触发的计数的逻辑，并且基于该计数识别突发的初始有效边缘。 由于在实际突发之前接收到的噪声或反射引起的任何错误选通都可以被拒绝。

公开(公告)号：US20140189224A1

公开(公告)日：2014-07-03

申请号：US13728581

申请日：2012-12-27

Applicant: ALEXEY KOSTINSKY ,  ZVIKA GREENFIELD ,  CHRISTOPHER P. MOZAK ,  PAVEL KONEV ,  OLGA FOMENKO

Inventor： ALEXEY KOSTINSKY ,  ZVIKA GREENFIELD ,  CHRISTOPHER P. MOZAK ,  PAVEL KONEV ,  OLGA FOMENKO

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

Abstract translation: 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 针脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。