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公开(公告)号：US12229590B2
公开(公告)日：2025-02-18
申请号：US17211852
申请日：2021-03-25
Applicant: Realtek Semiconductor Corp.
Inventor： Jhe-Yi Lin , Chun-Kai Tseng , Wen-Yung Lee , Shau-Yu Cheng
IPC: G06F9/48 , G06F9/30 , G06F9/50 , G06F16/901
Abstract: A content channel generation device comprises a resource unit assignment circuit, for assigning scheduled station(s) as node(s) of a full binary tree according to a search algorithm; a node computing circuit, for determining first node connection information of the full binary tree, and to determine second node connection information of a smallest full binary tree according to a smallest binary tree algorithm and the first node connection information; a load balance circuit, for determining user field numbers corresponding to content channels according to a load balance function and the second node connection information; a user field generation circuit, for generating a traversal result of the smallest full binary tree according to a traversal algorithm and the second node connection information, and for generating user fields corresponding to the content channels according to the traversal result, to generate the content channels.
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公开(公告)号：US20250045222A1
公开(公告)日：2025-02-06
申请号：US18791371
申请日：2024-07-31
Applicant: Realtek Semiconductor Corp.
Inventor： Chao-Min Lai
IPC: G06F13/20 , H04N21/4363
Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.
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公开(公告)号：US12211570B2
公开(公告)日：2025-01-28
申请号：US18129087
申请日：2023-03-31
Applicant: Realtek Semiconductor Corp.
Inventor： Li-Wei Deng , Ying-Yen Chen , Chih-Tung Chen
Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.
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公开(公告)号：US12206578B2
公开(公告)日：2025-01-21
申请号：US18385958
申请日：2023-11-01
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor： Chen-Wei Lee
Abstract: An aggregation packet forwarding method and a system for the same are provided. The method includes: configuring a first NIC to transmit to-be-forwarded packets to an aggregation module; configuring the aggregation module to generate an aggregated packet according to packet characteristics of the to-be-forwarded packets; configuring a first processing unit to execute a first NIC driver to process the aggregated packet generated by the aggregation module and send them to an L2 forwarding module; configuring the L2 forwarding module to transmit the aggregated packet according to an L2 forwarding table; configuring a second processing unit to execute a second NIC driver to process the aggregated packet and send the aggregated packet to a deaggregation module; configuring the deaggregation module to deaggregate the aggregated packet into the to-be-forwarded packets, and send the to-be-forwarded packets to the second NIC; and configuring the second NIC to receive the to-be-forwarded packets.
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公开(公告)号：US12205667B2
公开(公告)日：2025-01-21
申请号：US17954343
申请日：2022-09-28
Applicant: Realtek Semiconductor Corp.
Inventor： Sheng-Feng Chung
Abstract: The present invention provides a multi-die package including main die, a memory die, a first set of pins and a second set of pins. The main die includes a memory controller, a first set of pads, a second set of pads and a third set of pads. The memory die is coupled to the first set of pads and the second set of pads of the main die. The first set of pins is coupled to the third set of pads of the main die. The second set of pins is coupled to the second set of pads of the main die. The memory controller accesses the memory die through the first set of pads and the second set of pads, and the memory controller accesses a memory chip external to the multi-die package through the second set of pads and the third set of pads.
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Patent Agency Ranking
公开(公告)号：US20250013814A1
公开(公告)日：2025-01-09
申请号：US18668230
申请日：2024-05-19
Applicant: Realtek Semiconductor Corp.
Inventor： Wei-Ming Huang , Mei-Li Yu , Yu-Lan Lo
IPC: G06F30/392
Abstract: A method of an integrated circuit chip, includes: calculating a first slope of distance-to-spatial relation under first design condition according to spatial distance difference between two circuit elements within integrated circuit chip and a spatial process variation under first design condition; calculating a second slope of the distance-to-spatial relation under a second design condition according to the spatial distance difference and a spatial process variation under second design condition; calculating a ratio coefficient and an exponential coefficient according to the first slope, the second slope, a global process variation under the first design condition, and a global process variation under the second design condition; calculating a third slope of the distance-to-spatial relation under a third design condition according to the ratio coefficient and the exponential coefficient; and estimating a spatial process variation under the third design condition according to the third slope and the spatial distance difference.
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公开(公告)号：US12192645B2
公开(公告)日：2025-01-07
申请号：US18098175
申请日：2023-01-18
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor： Yu-Heng Tzeng
IPC: H04N23/73 , G06V10/25 , G06V10/50 , G06V10/60 , G06V10/75 , H04N23/741 , H04N25/589
Abstract: A method and a circuitry for exposure compensation applied to a high dynamic range video are provided. The circuitry is adapted to an image-acquisition device. In the method, when a video is received, the pixel values for each of the sequential frames can be obtained. Next, an exposure value ratio between two adjacent frames is obtained. A processor exposure value ratio of an image signal processor can be regarded as an initial exposure value ratio. A fixed adjustment ratio is used to control the image signal processor and an image sensor of the image-acquirement device so as to calculate an exposure value ratio for each of the frames. The exposure value ratio is referred to for performing the high dynamic range compensation for the frames so as to output an HDR video.
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公开(公告)号：US20250007458A1
公开(公告)日：2025-01-02
申请号：US18341854
申请日：2023-06-27
Applicant: Realtek Semiconductor Corp.
Inventor： Chia-Liang (Leon) Lin
IPC: H03B5/12
Abstract: An method of integrating an oscillator includes incorporating a main inductor and a main capacitor for establishing an oscillation; incorporating two cross-coupling NMOST and two cross-coupling PMOST for sustaining the oscillation; incorporating a first auxiliary inductor and a first auxiliary capacitor for suppressing a noise of the two cross-coupling NMOST; incorporating a second auxiliary inductor and a second auxiliary capacitor for suppressing a noise of the two cross-coupling PMOST; laying out the main inductor symmetrically with respect to a plane of symmetry; laying out the first auxiliary inductor as a parallel connection of two halves that are inside the main inductor and symmetrical with respect to the plane of symmetry; and laying out the second auxiliary inductor as a parallel connection of two halves that are inside the main inductor in a close proximity to the first auxiliary inductor and symmetrical with respect to the plane of symmetry.
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公开(公告)号：US20240406043A1
公开(公告)日：2024-12-05
申请号：US18660256
申请日：2024-05-10
Applicant: Realtek Semiconductor Corp.
Inventor： Tsung-Nan Yu
Abstract: The present invention provides a transceiver circuit, which includes a receiving circuit and a digital circuit, and the receiving circuit includes a first mixer, a second mixer, a bias voltage circuit, a complex filter and an ADC. In the operation of the transceiver circuit, the digital circuit controls the bias voltage circuit to sequentially switch the first bias voltage to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias values, wherein the plurality of first digital signals are used to calculate a plurality of first quality parameters respectively corresponding to the first bias values. The digital circuit controls the bias voltage circuit so that the first bias voltage has the first bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined according to the plurality of first quality parameters.
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公开(公告)号：US20240402754A1
公开(公告)日：2024-12-05
申请号：US18415595
申请日：2024-01-17
Applicant: Realtek Semiconductor Corp.
Inventor： I-Hsueh Lin , Pen-Ao Chen
IPC: G06F1/12
Abstract: A method for performing clock compensation in a communication device includes: determining a clock difference between a source operating clock and a target operating clock; performing clock compensation according to the clock difference, thereby obtaining a compensated time; and according to the compensated time, performing a clock synchronization process based on precision time protocol.
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