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公开(公告)号：US20240356326A1
公开(公告)日：2024-10-24
申请号：US18135935
申请日：2023-04-18
发明人： Isaac Y. CHEN
CPC分类号： H02H3/08 , H02H1/0007
摘要： An abnormal current protection device includes an overcurrent protector and a controller, and the overcurrent protector includes a short-circuit detection unit and an overcurrent detection unit. The short-circuit detection unit is configured to detect whether there is a short-circuit event within a period of debounce time of a protection cycle. The overcurrent detection unit is configured to detect whether there is an overcurrent event after the period of debounce time within the protection cycle. The controller is configured to disable a converter when the short-circuit event is detected, and disable a power stage when the overcurrent event is detected.
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公开(公告)号：US20240328853A1
公开(公告)日：2024-10-03
申请号：US18507115
申请日：2023-11-13
发明人： DAR-CHANG JUANG
CPC分类号： G01J1/44 , G01J1/0228 , H03F3/087 , G01J2001/444 , H03G3/3084
摘要： An active clamp photoelectric sensing device includes an input terminal, a first output terminal, a current-to-voltage conversion circuit, and an active clamp circuit. The input terminal receives an input current. The first output terminal outputs a first output voltage. The current-to-voltage conversion circuit is coupled between the input terminal and the first output terminal, and is used to discharge and lower potentials of the input terminal and the first output terminal to a first set voltage according to the state of a reset signal, or is used to gradually increase the first output voltage to a second set voltage. The active clamping circuit is coupled to the current-to-voltage conversion circuit, and is used to clamp the upper limit of the first output voltage to the second set voltage.
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公开(公告)号：US20240178796A1
公开(公告)日：2024-05-30
申请号：US18071581
申请日：2022-11-29
发明人： Isaac Y. Chen
CPC分类号： H03F1/0205 , H03F3/217 , H03F2200/03
摘要： An audio amplifier includes a plurality of power stages, a driving circuit, and a power stage control circuit. The driving circuit is arranged to drive the power stages. The power stage control circuit includes a feedback circuit and a control circuit. The feedback circuit is coupled to the power stages, and is arranged to generate a feedback signal according to at least one detection input, wherein the at least one detection input includes at least one of a power, a voltage signal corresponding to a switching time of the power stages, and a voltage signal corresponding to a switching frequency of the power stages. The control circuit is coupled between the feedback circuit and the power stages, and is arranged to generate a control signal according to the feedback signal, wherein the control signal is arranged to dynamically control a number of turned-on power stages in the power stages.
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公开(公告)号：US20240133934A1
公开(公告)日：2024-04-25
申请号：US17964847
申请日：2022-10-12
发明人： Yi-Chou Huang
CPC分类号： G01R27/2605 , H03F3/45475 , H03M3/30 , H03F2200/213 , H03F2200/271 , H03F2203/45156
摘要： A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.
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公开(公告)号：US11955163B2
公开(公告)日：2024-04-09
申请号：US17875449
申请日：2022-07-28
发明人： Po-Hsun Wu , Jen-Shou Hsu
IPC分类号： G11C11/408
CPC分类号： G11C11/4087
摘要： Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.
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公开(公告)号：US20240038293A1
公开(公告)日：2024-02-01
申请号：US17875449
申请日：2022-07-28
发明人： PO-HSUN WU , JEN-SHOU HSU
IPC分类号： G11C11/408
CPC分类号： G11C11/4087
摘要： Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.
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公开(公告)号：US20230421143A1
公开(公告)日：2023-12-28
申请号：US17847225
申请日：2022-06-23
发明人： Shu-Han Nien
CPC分类号： H03K5/135 , H03K5/2427 , H03K5/2418 , H03K2005/00176
摘要： An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
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公开(公告)号：US11777424B2
公开(公告)日：2023-10-03
申请号：US17494855
申请日：2021-10-06
发明人： Shih-Chieh Wang , Yong-Yi Jhuang , Ming-Fu Tsai
CPC分类号： H02P6/186 , H02P2207/05
摘要： A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.
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公开(公告)号：US11727968B2
公开(公告)日：2023-08-15
申请号：US17499870
申请日：2021-10-13
发明人： Po-Hsun Wu , Jen-Shou Hsu
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G11C7/225 , G11C2207/2254
摘要： A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.
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公开(公告)号：US20230237985A1
公开(公告)日：2023-07-27
申请号：US17583235
申请日：2022-01-25
发明人： HSIN-YUAN CHIU , HSIANG-YU YANG , YA-MIEN HSU
IPC分类号： G10K11/178 , H03G3/00
CPC分类号： G10K11/17813 , H03G3/001
摘要： An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.
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