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80 条记录 (耗时 0.023 秒)

    Code optimization conversations for connected managed runtime environments
    1.
    发明授权
    Code optimization conversations for connected managed runtime environments 有权

    公开(公告)号：US10552130B1

    公开(公告)日：2020-02-04

    申请号：US16004236

    申请日：2018-06-08

    申请人： Azul Systems, Inc.

    发明人： Gil Tene ,  Philip Reames

    IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F9/46 ,  G06F8/41 ,  G06F8/71 ,  G06F8/75

    摘要： A method of providing by a code optimization service an optimized version of a code unit to a managed runtime environment is disclosed. Information related to one or more runtime conditions associated with the managed runtime environment that is executing in a different process than that of the code optimization service is obtained, wherein the one or more runtime conditions are subject to change during the execution of the code unit. The optimized version of the code unit and a corresponding set of one or more speculative assumptions are provided to the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, wherein the set of one or more speculative assumptions are based on the information related to the one or more runtime conditions.

    CPU utilization metering on systems that include multiple hardware threads per core
    2.
    发明授权
    CPU utilization metering on systems that include multiple hardware threads per core 有权
    每个核心包含多个硬件线程的系统上的CPU利用率测量

    公开(公告)号：US09594659B2

    公开(公告)日：2017-03-14

    申请号：US14461172

    申请日：2014-08-15

    申请人： Azul Systems, Inc.

    发明人： Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    IPC分类号： G06F9/30 ,  G06F11/34

    CPC分类号： G06F11/3409 ,  G06F11/3423 ,  G06F2201/88

    摘要： Indicating usage in a system includes implementing a performance counter associated with one or more hardware threads; counting events associated with the one or more hardware threads to determine an event count; deriving an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count; applying a corrective function to modify the initial measure of usage and determine a modified measure of usage, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and outputting an indication of a processor usage, the indication being based at least in part on the modified measure of usage.

    摘要翻译： 指示系统中的使用包括实现与一个或多个硬件线程相关联的性能计数器; 与一个或多个硬件线程相关联的计数事件以确定事件计数; 至少部分地基于所述事件计数得出与所述一个或多个硬件线程相关联的处理器核心的使用的初始度量; 应用校正功能来修改初始使用度量并确定修改的使用度量，其中所述修改的使用度量具有不同于并不等同于所述使用的初始度量的值; 并且输出处理器使用的指示，所述指示至少部分地基于修改的使用度量。

    Resource allocation
    4.
    发明授权
    Resource allocation 有权
    资源分配

    公开(公告)号：US08589920B2

    公开(公告)日：2013-11-19

    申请号：US12586723

    申请日：2009-09-25

    申请人： Gil Tene ,  Shyam Prasad Pillalamarri

    发明人： Gil Tene ,  Shyam Prasad Pillalamarri

    IPC分类号： G06F9/455 ,  G06F9/46

    CPC分类号： G06F9/5077

    摘要： A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VMs is implemented in a plurality of core spaces. Each core VM is associated with one of a plurality of shell VMs. Resources of the core spaces are allocated among the core VMs.

    摘要翻译： 公开了一种用于执行分段虚拟机（VM）的技术。 在多个核心空间中实现多个核心VM。 每个核心VM与多个shell VM之一相关联。 核心空间的资源在核心虚拟机之间分配。

    Garbage collection with memory quick release
    5.
    发明授权
    Garbage collection with memory quick release 有权
    垃圾收集与内存快速释放

    公开(公告)号：US08452938B1

    公开(公告)日：2013-05-28

    申请号：US12082238

    申请日：2008-04-08

    申请人： Gil Tene ,  Michael A. Wolf

    发明人： Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0253 ,  G06F12/08

    摘要： Memory management includes identifying a region of virtual memory to be reclaimed, the region including at an object that is currently located at an original virtual memory location, and the region being supported by at least a portion of a memory resource; relocating the object from the original virtual memory location to a target virtual memory location; remapping one or more references to the object to the target virtual memory location; and releasing the portion of the memory resource prior to or contemporaneously with remapping the one or more references to the target location.

    摘要翻译： 存储器管理包括识别要回收的虚拟存储器的区域，该区域包括当前位于原始虚拟存储器位置处的对象，并且该区域由存储器资源的至少一部分支持; 将对象从原始虚拟内存位置重定位到目标虚拟内存位置; 将对象的一个​​或多个引用重新映射到目标虚拟存储器位置; 以及在将所述一个或多个引用重新映射到所述目标位置之前或同时释放所述存储器资源的所述部分。

    Segmented virtual machine transport mechanism
    6.
    发明授权
    Segmented virtual machine transport mechanism 有权
    分段虚拟机传输机制

    公开(公告)号：US08276138B2

    公开(公告)日：2012-09-25

    申请号：US12315854

    申请日：2008-12-05

    申请人： Gil Tene ,  Michael A. Wolf ,  Anirban Sengupta ,  Sivakumar Annamalai ,  Adrian Sun

    发明人： Gil Tene ,  Michael A. Wolf ,  Anirban Sengupta ,  Sivakumar Annamalai ,  Adrian Sun

    IPC分类号： G06F9/455 ,  G06F21/00

    CPC分类号： G06F9/544 ,  G06F9/45533

    摘要： Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.

    摘要翻译： 公开了向分段虚拟机（VM）上运行的应用提供数据。 提供数据包括打开分段的VM和外部数据源之间的接口，将数据从外部数据源传送到接口缓冲器，将第一选定数量的数据从接口缓冲器传送到壳VM缓冲器，传送第二选定量 的数据从shell VM缓冲区提供到核心VM缓冲区，以及响应于来自应用程序的读取请求，将数据从核心VM缓冲区提供给应用程序。

    Processor instruction used to determine whether to perform a memory-related trap
    9.
    发明授权
    Processor instruction used to determine whether to perform a memory-related trap 有权
    处理器指令用于确定是否执行内存相关的陷阱

    公开(公告)号：US07689782B1

    公开(公告)日：2010-03-30

    申请号：US11296195

    申请日：2005-12-06

    申请人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0253 ,  G06F9/30003

    摘要： An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

    摘要翻译： 公开了处理器在确定是否执行陷阱时使用的指令。 所述指令包括识别所述指令的一个或多个比特的第一组以及与所述确定中使用的第一地址值相关联的一个或多个比特的第二组。 该确定不包括执行使用第一地址值来确定存储器访问的存储器位置的存储器访问。 该确定至少部分地基于以下中的多于一个：包含在第一地址值中的一组或多个标记位的组，至少部分地使用第一地址值的一个或多个位的矩阵项， 与第一地址值相关联的翻译后备缓冲器条目，第一地址值是否与堆栈分配的存储器相关联，以及第一地址值是否包括空值。

    Array access
    10.
    发明授权
    Array access 有权
    阵列访问

    公开(公告)号：US07577801B1

    公开(公告)日：2009-08-18

    申请号：US11296191

    申请日：2005-12-06

    申请人： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    发明人： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0223 ,  G06F9/30043 ,  G06F9/345

    摘要： Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.

    摘要翻译： 访问阵列中的存储器包括执行第一指令，包括通过确定第一指令使用的索引是否在有效范围内，以及在索引在有效范围内的情况下，确定与阵列元素有关的存储器地址， 对应于索引。 如果索引在有效范围内，执行第二指令来访问数组元素，访问存储器还包括至少部分地基于由第一指令确定的存储器地址的访问。