公开(公告)号：US5347278A

公开(公告)日：1994-09-13

申请号：US129886

申请日：1993-09-30

申请人： Kent R. Callahan ,  Christopher J. Kemp

发明人： Kent R. Callahan ,  Christopher J. Kemp

IPC分类号： H03M3/02 ,  H03M5/06

CPC分类号： H03M5/06

摘要： A method for mapping the serial 0 and 1 pulses received at a known clock rate from a delta sigma modulator All 0's are generated at the output when no 11 pairs are present in the input signal during the sampled clock periods. A 1 is generated at the output responsive to the input signal and the input signal delayed by one clock period both being 1's when no 00 pairs are present in the input signal during the sampled clock periods. A 1 is generated at the output for each 11 pair not balanced by a 00 pair when 11 and 00 pairs are serially alternating in the input signal during the sampled clock periods. According to this mapping method, the pulse density of 1's in the output signal increases only responsive to an increase in the net number of 11 pairs in the input signal during the sampled clock periods. A circuit for implementing this pulse mapping method is also described.

摘要翻译： 在采样的时钟周期期间，当在输入信号中没有11对时，在输出端产生用于映射以已知时钟速率从ΔΣ调制器全部0接收的串行0和1脉冲的方法。 在输出端产生响应于输入信号和输入信号的输入信号A 1在输入信号期间在采样的时钟周期内不存在00对的情况下延迟一个时钟周期时为1的输出信号。 在采样时钟周期期间，当输入信号中11和00对串行交替时，在输出端产生一个不由00对平衡的每对11对的A 1。 根据该映射方法，输出信号中1的脉冲密度仅在采样时钟周期内响应于输入信号中的11对的净数量的增加而增加。 还描述了用于实现该脉冲映射方法的电路。

公开(公告)号：US5285459A

公开(公告)日：1994-02-08

申请号：US755761

申请日：1991-09-06

申请人： Yuzo Okuyama ,  Kazuo Sato ,  Yamato Tachibana ,  Ryuhei Motono ,  Kazuo Takeoka

发明人： Yuzo Okuyama ,  Kazuo Sato ,  Yamato Tachibana ,  Ryuhei Motono ,  Kazuo Takeoka

IPC分类号： H04L25/02 ,  H03M5/18 ,  H04L1/24 ,  H04L25/49 ,  G06F11/00 ,  H03M5/06 ,  H03M13/00

CPC分类号： H04L25/4925 ,  H03M5/18 ,  H04L1/247

摘要： An HDB3 code violation detector includes a converting part for receiving positive polarity data and negative polarity data from a PCM line and for converting an HDB3 code received via the PCM line into an NRZ signal, and a first judging part receiving the positive polarity data, the negative polarity data and the NRZ signal, for judging whether or not a pattern of the NRZ signal received from the converting part is possible when the NRZ signal is NRZ "1" and for outputting a judgement result. In addition, the detector includes a second judging part receiving the positive polarity data, the negative polarity data and the NRZ signal, for judging whether or not a pattern of the NRZ signal received from the converting part is possible when the NRZ signal has a maximum of three consecutive NRZ "0"s and for outputting a judgement result. Further, the detector includes a third judging part receiving the positive polarity data, the negative polarity data and the NRZ signal, for judging whether or not a pattern of the NRZ signal received from the converting part is possible when the NRZ signal has at least four consecutive NRZ "0"s and for outputting a judgement result, and a detecting part for detecting a code violation of the HDB3 code based on the judgement results of the first, second and third judging parts.

摘要翻译： HDB3代码违规检测器包括：转换部件，用于从PCM线路接收正极性数据和负极性数据，并将用于将经由PCM线路接收的HDB3代码转换为NRZ信号，以及接收正极性数据的第一判断部件， 负极性数据和NRZ信号，用于在NRZ信号为NRZ“1”时判断从转换部分接收到的NRZ信号的模式是否可能，并输出判断结果。 此外，检测器包括接收正极性数据，负极性数据和NRZ信号的第二判断部分，用于当NRZ信号具有最大值时判断从转换部分接收的NRZ信号的模式是否可能 的三个连续的NRZ“0”并输出判断结果。 此外，检测器包括接收正极性数据，负极性数据和NRZ信号的第三判断部分，用于当NRZ信号具有至少四个时，判断从转换部分接收的NRZ信号的模式是否可能 连续NRZ“0”，并输出判断结果，以及检测部，根据第一，第二，第三判断部的判定结果检测HDB3码的代码违例。

公开(公告)号：US5255128A

公开(公告)日：1993-10-19

申请号：US680361

申请日：1991-04-04

申请人： Hajime Inoue ,  Takahito Seki ,  Keiji Kanota

发明人： Hajime Inoue ,  Takahito Seki ,  Keiji Kanota

IPC分类号： G11B20/14 ,  G11B20/10 ,  H03M5/06 ,  H03M13/23 ,  H04N5/926 ,  H04N5/931 ,  G11B5/09

CPC分类号： H04N5/926 ,  G11B20/10009 ,  H04N5/931

摘要： In an apparatus for detecting input digital data, for example, as derived by analog-to-digital conversion of a reproduced binary signal in analog form; a distributor circuit distributes the input digital data into at least two channels, a processing circuit in each channel processes the respective digital data in accordance with a predetermined formula, a decoder in each channel decodes an output of the respective processing circuit in accordance with the Viterbi algorithm, and the outputs of the decoders are composed or combined to provide therefrom a single sequence of digital data.

公开(公告)号：US5113187A

公开(公告)日：1992-05-12

申请号：US673912

申请日：1991-03-25

申请人： Steven S. Gorshe

发明人： Steven S. Gorshe

IPC分类号： H03M5/06 ,  H03M5/12 ,  H03M5/14

CPC分类号： H03M5/12 ,  H03M5/14

摘要： A circuit having a completely synchronous and digital implementation for encoding a stream of digital data (NRZ form) into the coded marked inversion (CMI) format. The circuit includes a state machine having a predetermined number of defined legal and illegal states, an illegal state detection circuit, and an output circuit. When the state machine enters an illegal state because of, for example, the effects of noise or distortion on the digital data signal, the illegal state detection circuit forces the state machine back into a legal state.

摘要翻译： 具有完全同步和数字实现的电路，用于将数字数据流（NRZ形式）编码成编码标记反转（CMI）格式。 该电路包括具有预定数量的规定的合法和非法状态的状态机，非法状态检测电路和输出电路。 当状态机由于例如数字数据信号的噪声或失真的影响而进入非法状态时，非法状态检测电路迫使状态机恢复到合法状态。

公开(公告)号：US4870513A

公开(公告)日：1989-09-26

申请号：US908568

申请日：1986-09-18

申请人： Hermann Lia

发明人： Hermann Lia

IPC分类号： G11B5/09 ,  G11B20/10 ,  H03M5/06

CPC分类号： G11B20/10009 ,  G11B20/10

摘要： For the purpose of increasing storage density of data recorded on a magnetic recording medium, particularly on a magnetic tape, a coder stage is supplied with data signals allocated to the record data and with high-frequency magnetization signals. The coder stage generates write signals which are recorded with the magnetization signals. The pulse duration or the pulse pause of the respectively existing magnetization signal is lengthened given every change of the data signals. The magnetization signals and the data signals are preferably synchronized with one another such that the polarity of the magnetization of the recording medium changes at every change of the data signals. In the playback of the data, the peak values of the magnetization have zero axis crossings of the read output signals allocated to them. At the zero axis crossings, a detector stage generates data signals for a decoding of the recorded data.

摘要翻译： 为了增加记录在磁记录介质上，特别是磁带上的数据的存储密度，向编码器级提供分配给记录数据和高频磁化信号的数据信号。 编码器级产生用磁化信号记录的写入信号。 给定每个数据信号的变化时，脉冲持续时间或脉冲暂停时间延长。 磁化信号和数据信号优选地彼此同步，使得记录介质的磁化的极性在数据信号的每次改变时改变。 在数据的重放中，磁化的峰值具有分配给它们的读出的输出信号的零轴交叉。 在零轴交叉处，检测器级产生用于解码记录数据的数据信号。

公开(公告)号：US4750193A

公开(公告)日：1988-06-07

申请号：US40387

申请日：1987-04-20

申请人： James A. Bailey

发明人： James A. Bailey

IPC分类号： H03L7/08 ,  H03L7/089 ,  H03M5/06 ,  H04L7/033 ,  H04L25/40 ,  H03D3/24

CPC分类号： H04L7/033 ,  H03L7/0891

摘要： The data detector for extracting clock information from an encoded run length limited data signal, including a control loop comprised of a phase detector, the charge pump, a filter buffer circuit and a voltage-controlled oscillator, wherein the data detector embodies a monostable multivibrator having a Q2 output that changes from low to high state at one-half the duration of the Q1 output, so that the Q2 output lags Q1 by 90 degrees and appears in phase with the extracted clock signal when the loop is locked.

公开(公告)号：US4733404A

公开(公告)日：1988-03-22

申请号：US934879

申请日：1986-11-25

申请人： Vladimir E. Ostoich

发明人： Vladimir E. Ostoich

IPC分类号： H03K5/00 ,  H03L7/08 ,  H03M5/06 ,  H04L7/033 ,  H03D3/24 ,  H04L7/02

CPC分类号： H03L7/0807 ,  H04L7/033

摘要： A transmission control circuit for use in a data terminal equipment receiver section is disclosed. The output of a phase locked loop or narrow band tuned filter input register clocking circuit which includes a quasi-differentiator and full wave rectifier is sent to a divider circuit and the divided clocking signal is then quasi-differentiated, full-wave rectified and used to drive a signal source circuit. The signal source circuit output has a polarity which is determined by the signal output of the full wave rectifier and is integrated and fed back to control inputs of the quasi-differentiators. An offset signal is also provided to the integrator. The result is an automatic adjustment of the pulse width to a fixed fraction of the input bit period.

摘要翻译： 公开了一种用于数据终端设备接收器部分的传输控制电路。 包括准微分器和全波整流器的锁相环或窄带调谐滤波器输入寄存器时钟电路的输出被发送到除法器电路，然后分频时钟信号被准微分，全波整流并用于 驱动信号源电路。 信号源电路输出具有由全波整流器的信号输出确定的极性，并被积分并反馈给准微分器的控制输入。 还向积分器提供偏移信号。 结果是将脉冲宽度自动调整到输入位周期的固定分数。

公开(公告)号：US4598267A

公开(公告)日：1986-07-01

申请号：US604017

申请日：1984-04-26

申请人： Shinichi Fukuda

发明人： Shinichi Fukuda

IPC分类号： H03M5/06 ,  G11B20/14 ,  H03M7/14 ,  H04L25/49 ,  H03M7/20

CPC分类号： G11B20/1426

摘要： A converted digital signal is provided in NRZI code with a DC component of zero and with a maximum of four bits between level transitions in the signal by dividing the base digital signal into eight-bit base words, each of which is then converted into a ten-bit word signal that has 1024 (2.sup.10) possible combinations, of which there are 193 that begin with no more than two digital zeros, end with no more than one digital zero, have no more than three consecutive digital zeros anywhere else, and have a DC component of zero when NRZI coded, and each of which is used to represent one eight-bit base word. Each of the remaining 63 of the total 256 (2.sup.8) base words is converted into a secondary ten-bit combination having a "convention" DC component of +2 or -2. The number of level transitions in the converted, NRZI-coded digital signal are detected up to the end of the ten-bit combination immediately preceding the next secondary combination and, depending on the number of level changes, the first bit of the next secondary combination is provided to give it a convention DC component, thereby eliminating the DC component in that portion of the signal.

摘要翻译： 转换的数字信号以NRZI码提供，其中DC分量为零，并且通过将基本数字信号分成八位的基本字，将其分别转换成十位 具有1024（210）个可能组合的位字字信号，其中193个以不超过两个数字零开始，以不超过一个数字零结束，其他任何地方不得超过三个连续数字零，并具有 当NRZI编码时，DC分量为零，并且每个分量用于表示一个八位的基本字。 总共256（28）个基本字中的剩余63个中的每一个被转换为具有+2或-2的“约定”DC分量的辅助十位组合。 转换的NRZI编码的数字信号中的电平转换的数量被检测到直到紧接在下一个次级组合之前的十位组合的结尾，并且根据电平变化的数量，下一个次级组合的第一位 提供给它一个常规的DC分量，从而消除信号的该部分中的DC分量。

公开(公告)号：US20210232454A1

公开(公告)日：2021-07-29

申请号：US17229162

申请日：2021-04-13

申请人： Intel Corporation

发明人： Huimin Chen ,  Andrew Martwick ,  Howard Heck ,  Robert Dunstan ,  Dennis Bell ,  Abdul Ismail

IPC分类号： G06F11/10 ,  H03M5/06 ,  H03M5/12

摘要： Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

公开(公告)号：US20210224355A1

公开(公告)日：2021-07-22

申请号：US17301473

申请日：2021-04-05

申请人： Microsoft Technology Licensing, LLC

发明人： Ioan Alexandru STEFANOVICI ,  Benn Charles Thomsen ,  Alexander Lloyd Gaunt ,  Antony Ian Taylor Rowstron ,  Reinhard Sebastian Bernhard Nowozin

IPC分类号： G06F17/18 ,  G06F11/36 ,  G06N20/00 ,  G06F16/2458 ,  G11B20/10 ,  H03M13/37 ,  H03M5/06

摘要： Examples are disclosed that relate to encoding data on a data-storage medium. The method comprises obtaining a representation of a measurement performed on the data-storage medium, the representation being based on a previously recorded pattern of data encoded in the data-storage medium in a layout that defines a plurality of data locations. The method further comprises inputting the representation into a data decoder comprising a trained machine-learning function, and obtaining from the data decoder, for each data location of the layout, a plurality of probability values, wherein each probability value is associated with a corresponding data value and represents the probability that the corresponding data value matches the actual data value in the previously recorded pattern of data at a same location in the layout.