公开(公告)号：US20040041104A1

公开(公告)日：2004-03-04

申请号：US10457786

申请日：2003-06-10

Applicant: ASML NETHERLANDS B.V.

Inventor： Paulus Martinus Maria Liebregts ,  Arno Jan Bleeker ,  Erik Roelof Loopstra ,  Harry Borggreve

IPC: G21K005/10 ,  H01J037/08

CPC classification number: G03F7/70991 ,  G03F7/70291

Abstract: A lithographic apparatus uses the control signal from a computer to drive two spatial light modulators to pattern two separate projection beams for projection onto two substrates.

Abstract translation: 光刻设备使用来自计算机的控制信号来驱动两个空间光调制器来图案化两个分离的投影光束以投影到两个基板上。

公开(公告)号：US20030168617A1

公开(公告)日：2003-09-11

申请号：US09330154

申请日：1999-06-11

Inventor： SUSUMU GOTO

IPC: G21K005/10 ,  H01J037/08

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  G21K1/08 ,  H01J37/153 ,  H01J37/3174

Abstract: A projection apparatus includes a charged particle beam source, a reduction lens, a charged particle shaping aperture having an arcuate opening, a collimator lens, and first and second projection lenses. A charged particle beam emerging from the charged particle beam source irradiates a mask placed on a mask stage to transfer a pattern on the mask onto a sample on a sample stage. The first and second projection lenses can move their first and second principal plane positions with an excitation strength ratio control circuit. An image distortion amount is thus corrected.

Abstract translation: 投影装置包括带电粒子束源，还原透镜，具有弓形开口的带电粒子整形孔，准直透镜以及第一和第二投影透镜。 从带电粒子束源出射的带电粒子束照射放置在掩模台上的掩模，以将掩模上的图案转移到样品台上的样品上。 第一和第二投影透镜可以用激励强度比控制电路移动其第一和第二主平面位置。 因此校正图像失真量。

公开(公告)号：US20030122088A1

公开(公告)日：2003-07-03

申请号：US10294225

申请日：2002-11-14

Applicant: Varian Semiconductor Equipment Associates, Inc.

Inventor： Alan P. Sheng ,  Marvin R. LaFontaine

IPC: H01J037/08 ,  G21K005/10

CPC classification number: H01J37/3171 ,  H01J2237/20228 ,  H01J2237/30483

Abstract: An ion implanter is provided having an ion beam generator for generating an ion beam, a platen for holding a workpiece, such as a semiconductor wafer, and a tilt mechanism for tilting the platen and the wafer with respect to the ion beam. A scan controller mechanically moves the wafer and the platen relative to the ion beam so that the motion of the wafer and the platen is tangential, i.e. parallel, to the wafer surface. As a result, the ion beam intersects the wafer surface at a fixed position along the beamline as the wafer is scanned. The size and shape of the ion beam are thereby constant over all areas of the wafer surface during the implant for increasing implant uniformity.

Abstract translation: 提供离子注入机，其具有用于产生离子束的离子束发生器，用于保持诸如半导体晶片的工件的压板和用于相对于离子束倾斜压板和晶片的倾斜机构。 扫描控制器相对于离子束机械地移动晶片和压板，使得晶片和压板的运动与晶片表面是切线的，即平行的。 结果，当扫描晶片时，离子束在沿着束线的固定位置处与晶片表面相交。 因此，在植入期间，离子束的尺寸和形状在晶片表面的所有区域上都是恒定的，以增加植入物的均匀性。

公开(公告)号：US20030039895A1

公开(公告)日：2003-02-27

申请号：US10162391

申请日：2002-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yo-Han Choi

IPC: G03F009/00 ,  C23C014/00 ,  C23C014/32 ,  G03C005/00 ,  G21K005/10 ,  H01J037/08

CPC classification number: G03F1/84 ,  G03F1/74

Abstract: A photomask includes a mask substrate formed of a transparent nonconductor, a plurality of opaque conductive patterns formed on the mask substrate and separated from one another, and one or more conductive lines for connecting one of the conductive patterns with at least one adjacent conductive patterns. Electric charges, which accumulate in conductive patterns when using a focused ion beam (FIB) system, are dispersed through the conductive lines. The contrast of images of photomask patterns is increased by dispersion of electric charges, thereby improving the images of photomask patterns.

Abstract translation: 光掩模包括由透明非导体形成的掩模基板，形成在掩模基板上并彼此分离的多个不透明导电图案，以及用于将导电图案中的一个与至少一个相邻导电图案相连接的一条或多条导电线。 使用聚焦离子束（FIB）系统时积聚在导电图案中的电荷通过导线分散。 通过电荷的分散增加光掩模图案的图像的对比度，从而改善光掩模图案的图像。

公开(公告)号：US20020153493A1

公开(公告)日：2002-10-24

申请号：US10127729

申请日：2002-04-23

Applicant: Nissin Electric Co., Ltd

Inventor： Kenji Miyabayashi

IPC: H01J037/08

CPC classification number: H01J37/08 ,  H01J2237/31701

Abstract: An ion source vaporizer comprises a hollow vaporizer main body, a heater, and a nozzle. The hollow vaporizer main body has an opening portion. The heater is installed outside the vaporizer main body and evaporates a solid sample within the vaporizer main body. The nozzle feeds a vapor produced within the vaporizer main body into an arc chamber. The ion source vaporizer further comprises a crucible for filling the solid sample which is provided within a cavity of the vaporizer main body, and a pressing unit for pressing a crucible bottom against a cavity bottom of the vaporizer main body. One end of the nozzle is screwed with an upper part of the crucible.

Abstract translation: 离子源蒸发器包括中空蒸发器主体，加热器和喷嘴。 中空蒸发器主体具有开口部。 加热器安装在蒸发器主体外部，蒸发蒸发器主体内的固体样品。 喷嘴将在蒸发器主体内产生的蒸汽供给到电弧室中。 离子源蒸发器还包括用于填充设置在蒸发器主体的空腔内的固体样品的坩埚和用于将坩埚底部压靠在蒸发器主体的腔体底部的按压单元。 喷嘴的一端与坩埚的上部螺纹连接。

公开(公告)号：US20020148977A1

公开(公告)日：2002-10-17

申请号：US10173426

申请日：2002-06-18

Applicant: Hitachi, Ltd.

Inventor： Hiroyuki Tomita ,  Kazuo Mera

IPC: H01J037/08

CPC classification number: H01J37/3171 ,  H01J2237/20 ,  H01J2237/20228

Abstract: An ion implanter comprises an ion source and a wafer support device having a rotary disk that supports a plurality of wafers thereon and is rotated about its center axis, and capable of being swung alternately in opposite directions. An ion beam emitted by the ion source is projected on the wafers for ion implantation. The wafer support device is supported so that the center of gravity of the wafer support device lies below an axis about which the wafer support device is swung alternately in opposite directions and a component of the gravitational acceleration imparted to the wafer support device acts in the same direction as a force applied to the wafer support device to reverse the same.

公开(公告)号：US20020122989A1

公开(公告)日：2002-09-05

申请号：US09752887

申请日：2000-12-28

Inventor： Daniel G. Stearns ,  Donald W. Sweeney ,  Paul B. Mirkarimi

IPC: A61N005/00 ,  G21G005/00 ,  H01J037/08 ,  G21K005/10 ,  G03C005/00 ,  G03F009/00 ,  G03G016/00

CPC classification number: G03F1/34 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24

Abstract: Absorber material used in conventional EUVL reticles is eliminated by introducing a direct modulation in the complex-valued reflectance of the multilayer. A spatially localized energy source such as a focused electron or ion beam directly writes a reticle pattern onto the reflective multilayer coating. Interdiffusion is activated within the film by an energy source that causes the multilayer period to contract in the exposed regions. The contraction is accurately determined by the energy dose. A controllable variation in the phase and amplitude of the reflected field in the reticle plane is produced by the spatial modulation of the multilayer period. This method for patterning an EUVL reticle has the advantages of (1) avoiding the process steps associated with depositing and patterning an absorber layer and (2) providing control of the phase and amplitude of the reflected field with high spatial resolution.

Abstract translation: 通过在多层复数值的反射率中引入直接调制来消除用于常规EUVL标线的吸收材料。 诸如聚焦电子或离子束的空间局部化能源直接将掩模版图案写到反射多层涂层上。 相互扩散在膜内被能量源激活，导致多层周期在暴露区域中收缩。 收缩准确地由能量剂量确定。 通过多层周期的空间调制产生光罩平面中反射场的相位和幅度的可控变化。 用于图案化EUVL掩模版的方法具有以下优点：（1）避免与沉积和图案化吸收层相关的工艺步骤，以及（2）以高空间分辨率提供对反射场的相位和幅度的控制。

公开(公告)号：US20020094482A1

公开(公告)日：2002-07-18

申请号：US09766005

申请日：2001-01-18

Inventor： Scott M. Mansfield ,  Timothy A. Brunner ,  James A. Culp ,  Alfred K. Wong

IPC: H01J037/08 ,  G21K005/10 ,  G03C005/00 ,  G03F009/00

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70466 ,  H01J37/3026 ,  H01J2237/31761

Abstract: The present invention relates generally to a method for lithographically printing a mask pattern on a substrate, in particular a semiconductor substrate, wherein the mask pattern includes features with diverse pitches. These features may include device features such as vias or contact holes and lines in integrated circuits. The method comprises splitting the mask pattern into a plurality of masks, wherein one or more of the masks contains relatively tightly nested features and one or more of the masks contains relatively isolated features. Each of the plurality of masks is then successively exposed on a photoresist layer on the substrate. For each exposure, the exposure conditions, photoresist layer, other thin films layers, etching process, mask writing process, and/or mask pattern bias may be optimized for the tightly nested feature pattern or isolated feature pattern.

Abstract translation: 本发明一般涉及一种用于在基板上，特别是半导体衬底上光刻印刷掩模图案的方法，其中掩模图案包括具有不同间距的特征。 这些特征可以包括集成电路中的器件特征，例如通孔或接触孔和线。 该方法包括将掩模图案分成多个掩模，其中一个或多个掩模包含相对紧密嵌套的特征，并且一个或多个掩模包含相对孤立的特征。 然后将多个掩模中的每一个依次暴露在基板上的光致抗蚀剂层上。 对于每次曝光，曝光条件，光致抗蚀剂层，其它薄膜层，蚀刻工艺，掩模写入过程和/或掩模图案偏置可以针对紧密嵌套的特征图案或隔离的特征图案进行优化。

公开(公告)号：US20020090557A1

公开(公告)日：2002-07-11

申请号：US09431033

申请日：1999-11-01

Inventor： AKIHIRO SONODA

IPC: H01J037/08 ,  G21K005/10 ,  G03C005/00 ,  G03F009/00

CPC classification number: G03F1/36

Abstract: In order to provide a mask and a method for manufacturing a semiconductor device that achieve consistency in the resist pattern dimensions, a main pattern 110 provided for the purpose of semiconductor element production and an additional pattern 120 provided for the purpose of exposure quantity adjustment are drawn at a reticle 100. At the reticle 100, the additional pattern 120 achieves a regularity almost identical to that of the main pattern 110. At the same time, the additional pattern 120 has a specific shift relative to the main pattern 110. By achieving an optimal degree of shift between the additional pattern and main pattern at the reticle 100, consistency in the resist pattern dimensions can be achieved without adversely affecting the process of element pattern formation.

Abstract translation: 为了提供一种制造半导体器件的掩模和方法，其实现了抗蚀剂图案尺寸的一致性，绘制为了半导体元件制造而设置的主图案110和为曝光量调整目的而设置的附加图案120 在掩模版100处，附加图案120实现与主图案110的规则几乎相同的规则。同时，附加图案120具有相对于主图案110的特定位移。通过实现 在掩模版100处的附加图案和主图案之间的最佳偏移度可以在不影响元件图案形成的过程的情况下实现抗蚀剂图案尺寸的一致性。

公开(公告)号：US20020061471A1

公开(公告)日：2002-05-23

申请号：US09987928

申请日：2001-11-16

Applicant: NEC Corporation

Inventor： Masashi Fujimoto

IPC: G03F009/00 ,  G03C005/00 ,  H01J037/08 ,  G21K005/10

CPC classification number: G03F7/70333 ,  G03F1/30 ,  G03F7/70283 ,  G03F7/70466

Abstract: As a phase-shift mask 10, a positive type Levenson phase-shift mask is used. For example, a device having such a minimum line-width of about 100 nm as that of a gate layer circuit pattern 14 is exposed by a projection exposure apparatus using a KrF-Excimer laser as its light source. The circuit pattern 14 is formed by performing exposure twice using the phase-shift mask 10 and an ordinary mask 12 respectively. In this case, during the first time of exposure by use of the phase-shift mask 10, a substrate 141 is moved along an optical axis to expose the pattern onto a plurality of image-forming surfaces. By this multiple-focus exposure method, the errors in pattern dimensions can be averaged into a small value.

Abstract translation: 作为相移掩模10，使用正型Levenson相移掩模。 例如，使用KrF-Excimer激光器作为其光源的投影曝光装置曝光具有约100nm的栅极层电路图案14的最小线宽的器件。 通过使用相移掩模10和普通掩模12分别进行两次曝光来形成电路图案14。 在这种情况下，在通过使用相移掩模10的第一次曝光期间，基板141沿着光轴移动以将图案曝光到多个图像形成表面上。 通过该多焦点曝光方法，可以将图案尺寸中的误差平均化为小的值。