公开(公告)号：US20070002854A1

公开(公告)日：2007-01-04

申请号：US11171858

申请日：2005-06-30

Applicant: Alexander Smith

Inventor： Alexander Smith

IPC: H04J3/22 ,  H04J3/16 ,  H04J3/02 ,  H04L12/56 ,  H04L12/28

CPC classification number: H04L49/3027 ,  H04L49/1523 ,  H04L49/251 ,  H04L49/552

Abstract: In one embodiment, an apparatus comprises a switch fabric, an adaptation processor to append a length field to a received packet, and a switch fabric to use information in the length field to switch variable-sized packets.

Abstract translation: 在一个实施例中，一种装置包括交换结构，适配处理器，用于将长度字段附加到接收的分组，以及交换结构，以使用长度字段中的信息来切换可变大小的分组。

公开(公告)号：US20060285488A1

公开(公告)日：2006-12-21

申请号：US11467478

申请日：2006-08-25

Applicant: Masahiko Honda

Inventor： Masahiko Honda

IPC: H04J3/14 ,  H04L12/56

CPC classification number: H04L49/153 ,  H04L49/206 ,  H04L49/255 ,  H04L49/3027 ,  H04L49/552 ,  H04L2012/5627 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5681

Abstract: A packet switching system capable of ensuring the sequence and continuity of packets and further compensating for delays in transmission is disclosed. Each of two redundant switch sections has a high-priority queue and a low-priority queue for each of output ports. A high-priority output selector selects one of two high-priority queues corresponding to respective ones of the two switch sections to store an output of the selected one into a high-priority output queue. A low-priority output selector selects one of two low-priority queues corresponding to respective ones of the two switch sections to store an output of the selected one into a low-priority output queue. The high-priority and low-priority output selectors are controlled depending on a system switching signal and a packet storing status of each of the high-priority and low-priority queues.

Abstract translation: 公开了能够确保分组的序列和连续性并进一步补偿传输延迟的分组交换系统。 两个冗余交换机部分中的每一个具有用于每个输出端口的高优先级队列和低优先级队列。 高优先级输出选择器选择与两个切换部分中相应的两个切换部分相对应的两个高优先级队列中的一个，以将所选择的一个输出存储到高优先级输出队列中。 低优先级输出选择器选择与两个切换部分中相应的两个切换部分相对应的两个低优先级队列之一，以将所选择的一个输出存储到低优先级输出队列中。 高优先级和低优先级输出选择器根据系统切换信号和每个高优先级和低优先级队列的数据包存储状态进行控制。

公开(公告)号：US07142513B2

公开(公告)日：2006-11-28

申请号：US10155363

申请日：2002-05-23

Applicant: Yea-Li Sun ,  Jeng-Farn Lee

Inventor： Yea-Li Sun ,  Jeng-Farn Lee

IPC: H04L12/54

CPC classification number: H04L47/20 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/522 ,  H04L47/6215 ,  H04L47/623 ,  H04L49/20 ,  H04L49/30 ,  H04L49/3027 ,  H04L49/503

Abstract: In a method and multi-queue packet scheduling system for managing network packet traffic, each of a plurality of output buffer queues is assigned with a reserved weight in bandwidth sharing of an output link, is associated with a respective service class, and may be optionally assigned with a maximum rate to constrain packet transmission therethrough. The output buffer queues are adapted for enqueueing incoming packets therein according to associated service classes of the incoming packets. A shared bandwidth rate calculator determines in real-time shared bandwidth rates of maximum-rate constrained backlogged output buffer queues with reference to the reserved weights and such that the shared bandwidth rates do not exceed the assigned maximum rates. A packet scheduler transmits outgoing packets from the backlogged output buffer queues in accordance with a schedule that is based on the shared bandwidth rates determined by the shared bandwidth rate calculator.

公开(公告)号：US20060256783A1

公开(公告)日：2006-11-16

申请号：US11400367

申请日：2006-04-06

Applicant: Robert Ayrapetian ,  Edward Ayrapetian ,  Serob Douvalian

Inventor： Robert Ayrapetian ,  Edward Ayrapetian ,  Serob Douvalian

IPC: H04L12/50 ,  H04L12/56

CPC classification number: H04L49/3036 ,  H04L49/101 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3027 ,  H04L49/3045 ,  H04L49/503

Abstract: A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

公开(公告)号：US20060248376A1

公开(公告)日：2006-11-02

申请号：US11395570

申请日：2006-03-31

Applicant: Bertan Tezcan ,  William Beane ,  Scott Darnell

Inventor： Bertan Tezcan ,  William Beane ,  Scott Darnell

IPC: G06F11/00

CPC classification number: H04L49/30 ,  H04L45/52 ,  H04L47/70 ,  H04L49/10 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/3063 ,  H04L49/35

Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

Abstract translation: 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 芯片还包括可配置为从接收到的分组的有效载荷中提取数据的分组处理器，以处理所提取的数据以产生具有与外部接收者的数据结构兼容的格式的有效载荷的新分组，并将新分组传送到输出端口 。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。

公开(公告)号：US20060221948A1

公开(公告)日：2006-10-05

申请号：US11095269

申请日：2005-03-31

Applicant: Alan Benner ,  Cyriel Minkenberg ,  Craig Stunkel

Inventor： Alan Benner ,  Cyriel Minkenberg ,  Craig Stunkel

IPC: G01R31/08 ,  H04L12/26 ,  H04J3/14 ,  H04J1/16 ,  H04L1/00

CPC classification number: H04L47/10 ,  H04L47/266 ,  H04L47/39 ,  H04L49/15 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/505

Abstract: The interconnecting network for switching data packets, having data and flow control information, comprises a local packet switch element (S1) with local input buffers (I(1,1) . . . I(1,y)) for buffering the incoming data packets, a remote packet switch element (S2) with remote input buffers (I(2,1) . . . I(2,y)) for buffering the incoming data packets, and data lines (L) for interconnecting the local and the remote packet switch elements (S1, S2). The interconnecting network further comprises a local and a remote arbiter (A1, A2) which are connected via control lines (CL) to the input buffers (I(1,1) . . . I(1,y), I(2,1) . . . I(2,y)), and which are formed such that they can provide that the flow control information is transmitted via the data lines (L) and the control lines (CL).

Abstract translation: 用于切换具有数据和流控制信息的数据分组的互连网络包括本地分组交换单元（S1），其具有本地输入缓冲器（I（1,1）... I（1，y）），用于缓冲输入 数据分组，用于缓冲输入数据分组的远程分组交换单元（S 2）和用于互连本地的数据线（L）的远程输入缓冲器（I（2,1）... I（2，y）） 和远程分组交换单元（S1，S2）。 互连网络还包括本地和远程仲裁器（A 1，A 2），其通过控制线路（CL）连接到输入缓冲器（I（1,1）... I（1，y），I（ 2,1）... I（2，y）），并且它们被形成为使得它们可以提供经由数据线（L）和控制线（CL）传输流量控制信息。

公开(公告)号：US20060176893A1

公开(公告)日：2006-08-10

申请号：US11326326

申请日：2006-01-06

Applicant: Yoon-Jin Ku ,  Jong-Sang Oh ,  Byung-Chang Kang ,  Yong-Seok Park

Inventor： Yoon-Jin Ku ,  Jong-Sang Oh ,  Byung-Chang Kang ,  Yong-Seok Park

IPC: H04L12/56

CPC classification number: H04L49/9047 ,  H04L49/3027 ,  H04L49/557 ,  H04L49/90 ,  H04L49/9057

Abstract: In a method of dynamic queue management for stable packet forwarding and a network processor element therefor, a network processor of a switch/router can stably assign a packet descriptor for packet forwarding of a local area network/wide are network (LAN/WAN) interface. The method comprises the steps of: determining whether there is a corrupted link for the purpose of processing packets for the forwarding; setting free a packet buffer and a descriptor stored in a queue of a port corresponding to the corrupted link; detecting a normal link to number corresponding output ports; and queuing the packets and descriptors corresponding to the packets to a forwarded one of the calculated ports.

Abstract translation: 在用于稳定分组转发的动态队列管理方法及其网络处理器元件中，交换机/路由器的网络处理器可以稳定地分配用于局域网/广域网（LAN / WAN）接口的分组转发的分组描述符 。 该方法包括以下步骤：为了处理用于转发的分组的目的，确定是否存在损坏的链路; 设置一个分组缓冲区和存储在对应于被破坏的链路的端口队列中的描述符; 检测到对应输出端口号码的正常链路; 并将与分组对应的分组和描述符排队到所计算的转发的端口之一。

公开(公告)号：US20060129525A1

公开(公告)日：2006-06-15

申请号：US10538563

申请日：2003-11-18

Applicant: Edwin Rijpkema

Inventor： Edwin Rijpkema

IPC: G06F17/30

CPC classification number: H04L47/52 ,  H04L47/2408 ,  H04L47/50 ,  H04L49/101 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90

Abstract: A data switching device has inputs for Granted Throughput (GT) and Best Effort (BE) data, outputs, a data switch interconnecting the inputs and outputs, (GT) control means for controlling the (GT) data scheduling and (BE) control means for controlling the (BE) data scheduling. The (GT) and (BE) control means are arranged for a combined control such that the (BE) data scheduling is based on a contention free (GT) scheduling.

Abstract translation: 数据交换装置具有用于授权吞吐量（GT）和最佳努力（BE）数据的输入，输出互连输入和输出的数据交换机，（GT）控制装置，用于控制（GT）数据调度和（BE）控制装置 用于控制（BE）数据调度。 （GT）和（BE）控制装置被布置为组合控制，使得（BE）数据调度基于无竞争（GT）调度。

公开(公告)号：US07035273B1

公开(公告)日：2006-04-25

申请号：US10071417

申请日：2002-02-06

Applicant: Donald Pannell ,  Hugh Walsh

Inventor： Donald Pannell ,  Hugh Walsh

IPC: H04L12/54

CPC classification number: H04L47/32 ,  H04L47/24 ,  H04L47/29 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/901

Abstract: In general, in one aspect, the invention features a method, apparatus, and computer-readable media for sending a frame of data from a first channel to a second channel using at least one of m memory buffers for storing a frame, m being at least 2, in which n of the m buffers have an available status and p of the m buffers have an unavailable status, wherein m=n+p. It comprises reserving q of the n buffers having the available status to the first channel; reserving r of the n buffers having the available status to the second channel, wherein q+r≦n; when a frame is received from the first channel, storing the frame in i of the q buffers, wherein 1≦i≦q, and changing status of the i buffers to unavailable; selectively assigning the frame to the second channel based on a number s of the q buffers, wherein s≦q; and wherein if the frame is assigned to the second channel, the frame is sent to the second channel from the i buffers and the status of the i buffers is changed to available; and if the frame is not assigned to the second channel, the frame is discarded and the status of the i buffers is changed to available.

Abstract translation: 通常，一方面，本发明的特征在于一种用于使用m个存储器缓冲器中的至少一个来将数据帧从第一通道发送到第二通道的方法，装置和计算机可读介质，用于存储帧，m处于 至少2，其中m个缓冲器中的n个具有可用状态，并且m个缓冲器的p具有不可用状态，其中m = n + p。 它包括将具有可用状态的n个缓冲器的q保留到第一信道; 将具有可用状态的n个缓冲器的r保留到第二信道，其中q + r <= n; 当从第一信道接收到帧时，将帧存储在q个缓冲器的i中，其中1≤i≤Q，并且将i缓冲器的状态改变为不可用; 基于q个缓冲器的数量s，选择性地将帧分配给第二信道，其中s = q; 并且其中如果所述帧被分配给所述第二信道，则将所述帧从所述i个缓冲器发送到所述第二信道，并且所述i个缓冲器的状态被改变为可用的; 并且如果帧未被分配给第二信道，则丢弃该帧并且将i缓冲器的状态改变为可用的。

公开(公告)号：US07035212B1

公开(公告)日：2006-04-25

申请号：US09770832

申请日：2001-01-25

Applicant: Millind Mittal ,  Laxman Shankar

Inventor： Millind Mittal ,  Laxman Shankar

IPC: H04L12/28

CPC classification number: H04L49/254 ,  H04L45/60 ,  H04L47/2441 ,  H04L49/201 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/3027

Abstract: An end to end forwarding architecture includes a memory hub having a first ingress interface for receiving packets from a source port. The packets have associated ingress flow identifiers. A second ingress interface outputs the packets to a switch fabric. An ingress controller manages how the packets are queued and output to the switch fabric. The same memory hub can be used for both per flow queuing and per Class of Service (CoS) queuing. A similar structure is used on the egress side of the switch fabric. The end to end forwarding architecture separates per flow traffic scheduling operations performed in a traffic manager from the per flow packet storage operations performed by the memory hub.

Abstract translation: 端对端转发架构包括具有用于从源端口接收分组的第一入口接口的存储器集线器。 数据包具有相关的入口流标识符。 第二个入口接口将数据包输出到交换结构。 入口控制器管理数据包如何排队并输出到交换结构。 每个流队列和每个服务等级（CoS）队列都可以使用相同的内存集线器。 在交换结构的出口侧使用类似的结构。 端到端转发架构根据由存储器集线器执行的每个流分组存储操作在流量管理器中执行的每个流量调度操作分离。