公开(公告)号：US20220246441A1

公开(公告)日：2022-08-04

申请号：US17723133

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Chai-Wei Chang ,  Bo-Feng Young ,  Chia-Yang Liao

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213

Abstract: A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.

公开(公告)号：US20220208990A1

公开(公告)日：2022-06-30

申请号：US17699994

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US20220173115A1

公开(公告)日：2022-06-02

申请号：US17674422

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/11514 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.

公开(公告)号：US20220122887A1

公开(公告)日：2022-04-21

申请号：US17567586

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L21/8239 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

公开(公告)号：US20210408043A1

公开(公告)日：2021-12-30

申请号：US17106516

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L21/28 ,  H01L29/78

Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

公开(公告)号：US20210407569A1

公开(公告)日：2021-12-30

申请号：US17064279

申请日：2020-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

公开(公告)号：US20210375940A1

公开(公告)日：2021-12-02

申请号：US17070619

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/12 ,  H01L21/84

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

公开(公告)号：US20210226066A1

公开(公告)日：2021-07-22

申请号：US16745340

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Chien-Ning Yao

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.

公开(公告)号：US20210202697A1

公开(公告)日：2021-07-01

申请号：US16806366

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

公开(公告)号：US20210126099A1

公开(公告)日：2021-04-29

申请号：US16798440

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi-On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets.