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公开(公告)号：US12046839B2
公开(公告)日：2024-07-23
申请号：US17629417
申请日：2021-04-12
CPC classification number: H01Q9/0421 , H01Q1/22 , H01Q1/48 , H01Q1/50 , H01Q9/04
Abstract: An antenna structure includes a dielectric substrate, a ground layer and a radiation layer located at two opposite sides of the dielectric substrate. The ground layer has two first gaps which are symmetrical about a central axis of the antenna structure in a first direction to introduce a radiation zero. The radiation layer has two second gaps which are symmetrical about the central axis, edges of the two second gaps are aligned with edges of the radiation layer in a second direction to introduce another radiation zero. The second direction is perpendicular to the first direction.
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公开(公告)号：US12034013B2
公开(公告)日：2024-07-09
申请号：US17594832
申请日：2020-12-21
Inventor： Chongyang Zhao , Yingmeng Miao , Zhihua Sun , Feng Qu , Xiaochun Xu
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/1244 , G02F1/136286 , G02F1/13625 , G02F1/136295 , G02F1/1368 , H01L27/1288
Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.
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公开(公告)号：US11996610B2
公开(公告)日：2024-05-28
申请号：US17605630
申请日：2020-11-10
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yali Wang , Dongdong Zhang , Feng Qu
Abstract: The present disclosure provides an antenna and a manufacturing method thereof, and belongs to the field of communication technology. The antenna provided by an embodiment of the present disclosure includes: a first substrate and a second substrate opposite to each other, a dielectric layer provided therebetween, and a feed unit on a side of the second substrate away from the first substrate. The first substrate includes: a first base substrate; and a radiation unit on a side of the first base substrate close to the second substrate. The second substrate includes: a second base substrate; and a reference electrode layer on a side of the second base substrate away from the feed unit, the reference electrode layer has an opening, an orthographic projection of the opening on the second base substrate is at least partially overlapped with an orthographic projection of the radiation unit on the second base substrate.
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公开(公告)号：US11988925B2
公开(公告)日：2024-05-21
申请号：US17432557
申请日：2020-10-28
Inventor： Min He , Jing Wang , Xiaodong Xie , Tianyu Zhang , Xue Zhao , Tengfei Zhong , Xinxiu Zhang , Huayu Sang , Feng Qu
IPC: G02F1/1345
CPC classification number: G02F1/1345
Abstract: The embodiment of the present disclosure provides a driving backplate including a base substrate, and an insulation layer and a plurality of conductive structures on the base substrate. The insulation layer insulates the plurality of conductive structures from each other. The plurality of conductive structures includes a first conductive layer and a second conductive layer sequentially stacked along a direction away from the base substrate. At least one portion of a region in which the first conductive layer is in contact with the second conductive layer includes a flat contact region. An opening is formed at a position in the insulation layer corresponding to the conductive structure. An edge of the opening in the insulation layer is between the first conductive layer and the second conductive layer and is correspondingly in edge regions of the first conductive layer and the second conductive layer.
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公开(公告)号：US11934070B2
公开(公告)日：2024-03-19
申请号：US17600162
申请日：2020-10-23
Inventor： Quan Gan , Ya Yu , Feng Qu , Yongcan Wang , Fengzhen Lv , Xianjie Shao , Rui Ma
IPC: G02F1/1339 , G02F1/1335
CPC classification number: G02F1/13394 , G02F1/133512 , G02F1/13396
Abstract: Disclosed is a display panel including: first spacer on the array substrate, an orthographic projection of the first spacer on the array substrate being a first pattern extending along a first direction; a second spacer on the counter substrate, an orthographic projection of the second spacer on the array substrate being a second pattern extending along a second direction; at least two third spacers, orthographic projections of which on the array substrate being respectively on two sides of the first pattern along the first direction; at least two fourth spacers, orthographic projections of which on the array substrate being respectively on two sides of the second pattern along the second direction; one of the third spacer and the fourth spacer is on the array substrate, and the other is on the counter substrate.
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Patent Agency Ranking
公开(公告)号：US11881631B2
公开(公告)日：2024-01-23
申请号：US17621126
申请日：2021-02-26
Inventor： Qianhong Wu , Jingwen Guo , Chunxin Li , Jia Fang , Feng Qu
Abstract: An antenna includes: a substrate; a first reference electrode on a first surface of the substrate; a radiating element on a second surface of the substrate, feeding directions of a first port and a second port of the radiating element are different; and at least one transmission structure on the second surface of the substrate and connected to at least one of the first port and the second port. The transmission structure includes: a signal electrode, a second reference electrode on at least one side of the signal electrode, and at least one membrane bridge; the signal electrode feeds a microwave signal into the radiating element, is positioned in a space surrounded by the membrane bridge and the substrate, and is insulated from the membrane bridge through an interlayer dielectric layer; orthographic projections of the membrane bridge and the second reference electrode on the substrate are overlapped.
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公开(公告)号：US11876274B2
公开(公告)日：2024-01-16
申请号：US17443566
申请日：2021-07-27
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jingwen Guo , Chunxin Li , Qianhong Wu , Yanzhao Li , Feng Qu
Abstract: A phase shifter and an antenna device are provided. The phase shifter includes a substrate, a signal line on the substrate, ground lines in pairs on the substrate, and a capacitance adjusting component. Two ground lines in a same pair of ground lines are on both sides of the signal line and spaced apart from the signal line, respectively. The capacitance adjusting component includes a film bridge, and both ends of the film bridge are on the two ground lines, respectively. The signal line is in a space enclosed by the film bridge and the substrate. The capacitance adjusting component is configured to adjust a capacitance between the film bridge and the signal line to a target capacitance when the capacitance adjusting component receives a bias voltage, and the target capacitance has a linear correlation with a magnitude of the bias voltage.
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公开(公告)号：US11783744B2
公开(公告)日：2023-10-10
申请号：US17445810
申请日：2021-08-24
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1≤k≤K≤N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n−i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1
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公开(公告)号：US20230196961A1
公开(公告)日：2023-06-22
申请号：US18082691
申请日：2022-12-16
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yangping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0267 , G09G2300/0408 , G09G2310/08 , G09G2300/08 , G09G2310/0243 , G09G2310/0286
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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公开(公告)号：US11636793B2
公开(公告)日：2023-04-25
申请号：US17341756
申请日：2021-06-08
Inventor： Zhihua Sun , Yinlong Zhang , Qiujie Su , Feng Qu , Jing Liu , Yanping Liao , Xibin Shao
IPC: G09G3/20
Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.
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