公开(公告)号：US20170286322A1

公开(公告)日：2017-10-05

申请号：US15271102

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1441 ,  G06F12/1081 ,  G06F2212/1052

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US20160364350A1

公开(公告)日：2016-12-15

申请号：US15011291

申请日：2016-01-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Abstract translation: 在处理器间通信（IPC）链路上进行同步多方向传输的方法和装置。 在一个实施例中，同步多向​​传输利用被配置为在第一状态期间累积数据的一个或多个缓冲器。 一个或多个缓冲器还被配置为在第二状态期间传送累积的数据。 在一个或多个处理器不活动的低功率状态期间，数据被累积，并且数据传输在处理器处于活动状态的操作状态期间发生。 此外，在一些变型中，可以对当前可用的传输资源执行数据传输，并且停止直到额外的传输资源可用。 在其他变型中，一个或多个可独立操作的处理器可以执行流量监控过程，以便优化IPC链路的数据吞吐量。

公开(公告)号：US20160103689A1

公开(公告)日：2016-04-14

申请号：US14879024

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

公开(公告)号：US20140064167A1

公开(公告)日：2014-03-06

申请号：US13755743

申请日：2013-01-31

Applicant: APPLE INC.

Inventor： Karan Sanghi ,  Ben-Heng Juang ,  Arjuna Sivasithambaresan

IPC: H04W52/02

CPC classification number: H04W52/0209 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/164

Abstract: A method includes inter-chip data communications between a power-managed integrated circuit (IC) and a peer IC. The peer IC generates a data frame and prepends a discardable preamble of a predefined size to a payload of the data frame. The predefined size is a size not less than a size of data discarded by the power-managed IC upon the power-managed IC receiving a data frame while in a low-power state. The peer IC transmits the data frame to the power-managed IC. The power-managed IC, while in a low-power state, may receive the data frame from the peer IC and in response to receiving the data frame, begin exiting the low-power state. The power-managed IC, while exiting the low-power state, may discard a portion of the data frame such as for example, some or all of the discardable preamble, without discarding payload.

Abstract translation: 一种方法包括功率管理集成电路（IC）和对等IC之间的片间数据通信。 对等IC产生数据帧，并将预定义大小的可丢弃前导码添加到数据帧的有效载荷。 在功率管理IC在低功率状态下接收数据帧时，预定义的尺寸是不小于功率管理IC所丢弃的数据的大小的尺寸。 对等IC将数据帧发送到功率管理IC。 功率管理IC在处于低功率状态时可以从对等IC接收数据帧，并且响应于接收到数据帧，开始退出低功率状态。 功率管理IC在退出低功率状态时可以丢弃数据帧的一部分，例如可丢弃的前导码中的一些或全部，而不丢弃有效载荷。